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Revision 8
ProASIC3 nano Flash FPGAs
Features and Benefits
Wide Range of Features
* 10 k to 250 k System Gates * Up to 36 kbits of True Dual-Port SRAM * Up to 71 User I/Os
(R)
Advanced I/Os
* 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation * Bank-Selectable I/O Voltages--up to 4 Banks per Chip * Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V * Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V * I/O Registers on Input, Output, and Enable Paths * Selectable Schmitt Trigger Inputs * Hot-Swappable and Cold-Sparing I/Os * Programmable Output Slew Rate and Drive Strength * Weak Pull-Up/-Down * IEEE 1149.1 (JTAG) Boundary Scan Test * Pin-Compatible Packages across the ProASIC3 Family * Up to Six CCC Blocks, One with an Integrated PLL * Configurable Phase Shift, Multiply/Divide, Delay Capabilities and External Feedback * Wide Input Frequency Range (1.5 MHz to 350 MHz)
Reprogrammable Flash Technology
* 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process * Live at Power-Up (LAPU) Level 0 Support * Single-Chip Solution * Retains Programmed Design when Powered Off
High Performance
* 350 MHz System Performance
In-System Programming (ISP) and Security
* Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532-compliant) * FlashLock(R) to Secure FPGA Contents
Clock Conditioning Circuit (CCC) and PLL
Low Power
* * * *
Embedded Memory
* 1 kbit of FlashROM User Nonvolatile Memory * SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations) * True Dual-Port SRAM (except x18 organization)
Low Power ProASIC(R)3 nano Products 1.5 V Core Voltage for Low Power Support for 1.5 V-Only Systems Low-Impedance Flash Switches
High-Performance Routing Hierarchy
* Segmented, Hierarchical Routing and Clock Structure
Enhanced Commercial Temperature Range
* -20C to +70C
Table 1 * ProASIC3 nano Devices
ProASIC3 nano Devices ProASIC3 nano-Z Devices System Gates Typical Equivalent Macrocells VersaTiles (D-flip-flops) RAM Kbits (1,024 bits)2 4,608-Bit Blocks
2
A3PN010
A3PN015
A3PN020 A3PN030Z1
A3PN060
A3PN125
A3PN250 A3N250Z 250,000 2,048 6,144 36 8 1 Yes 1 18 4 68 68
A3PN060Z A3PN125Z 60,000 512 1,536 18 4 1 Yes 1 18 2 71 71 125,000 1,024 3,072 36 8 1 Yes 1 18 2 71 71
10,000 86 260 - - 1 - - 4 2 34 34 QN48
15,000 128 384 - - 1 - - 4 3 49 - QN68
20,000 172 520 - - 1 - - 4 3 49 52 QN68
30,000 256 768 - - 1 - - 6 2 77 83 QN48, QN68 VQ100
FlashROM Kbits Secure (AES) ISP2 Integrated PLL in CCCs2 VersaNet Globals I/O Banks Maximum User I/Os (packaged device) Maximum User I/Os (Known Good Die) Package Pins QFN VQFP
VQ100
VQ100
VQ100
Notes: 1. A3PN030 is available in the Z feature grade only. 2. A3PN030 and smaller devices do not support this feature. 3. For higher densities and support of additional features, refer to the ProASIC3 and ProASIC3E datasheets.
A3PN030 and smaller devices do not support this feature.
April 2010 (c) 2010 Actel Corporation
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ProASIC3 nano Flash FPGAs
I/Os Per Package
ProASIC3 nano Devices ProASIC3 nano-Z Devices Known Good Die QN48 QN68 VQ100 34 34 - - - - 49 - 52 - 49 - A3PN010 A3PN015 A3PN020 A3PN030Z 1 83 34 49 77 A3PN060 A3PN060 71 - - 71 A3PN125 A3PN125Z 71 - - 71 A3PN250 A3PN250Z 68 - - 68
Notes: 1. A3PN030 is available in the Z feature grade only. 2. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 FPGA Fabric User's Guide to ensure compliance with design and board migration requirements. 3. "G" indicates RoHS-compliant packages. Refer to "ProASIC3 nano Ordering Information" on page III for the location of the "G" in the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other packages are RoHS-compliant only. Table 2 * ProASIC3 nano FPGAs Package Sizes Dimensions Packages Length x Width (mm\mm) Nominal Area (mm2) Pitch (mm) Height (mm) QN48 6x6 36 0.4 0.90 QN68 8x8 64 0.4 0.90 VQ100 14 x 14 196 0.5 1.20
ProASIC3 nano Device Status
ProASIC3 nano Devices A3PN010 A3PN015 A3PN020 Status Production Production Production A3PN030Z A3PN060 A3PN125 A3PN250 Advance Advance Production A3PN060Z A3PN125Z A3PN250Z Production Advance Advance Production ProASIC3 nano-Z Devices Status
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ProASIC3 nano Flash FPGAs
ProASIC3 nano Ordering Information
A3PN250 _ Z 1 VQ G 100 I Application (Temperature Range) Blank = Commercial (-20C to +70C Ambient Temperature) I = Industrial (-40C to +85C Ambient Temperature) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant Packaging Package Type QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches) VQ = Very Thin Quad Flat Pack (0.5 mm pitch) DIELOT = Known Good Die Speed Grade Blank = Standard 1 = 15% Faster than Standard 2 = 25% Faster than Standard Feature Grade Z = nano devices without enhanced features Blank = Standard Part Number ProASIC3 nano Devices A3PN010 = 10,000 System Gates A3PN015 = 15,000 System Gates A3PN020 = 20,000 System Gates A3PN030 = 30,000 System Gates A3PN060 = 60,000 System Gates A3PN125 = 125,000 System Gates A3PN250 = 250,000 System Gates
*
Note: *For the A3PN060, A3PN125, and A3PN250, the Z feature grade does not support the enhanced nano features of Schmitt trigger input, cold-sparing, and hot-swap I/O capability. The A3PN030 Z feature grade does not support Schmitt trigger input. For the VQ100, CS81, UC81, QN68, and QN48 packages, the Z feature grade and the N part number are not marked on the device.
Device Marking
Actel normally topside marks the full ordering part number on each device. There are some exceptions to this, such as some of the Z feature grade nano devices, the V2 designator for IGLOO devices, and packages where space is physically limited. Packages that have limited characters available are UC36, UC81, CS81, QN48, QN68, and QFN132. On these specific packages, a subset of the device marking will be used that includes the required legal information and as much of the part number as allowed by character limitation of the device. In this case, devices will have a truncated device marking and may exclude the applications markings, such as the I designator for Industrial Devices or the ES designator for Engineering Samples.
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III
ProASIC3 nano Flash FPGAs Figure 1 shows an example of device marking based on the AGL030V5-UCG81. The actual mark will vary by the device/package combination ordered.
Device Name (six characters) Package
Wafer Lot #
ACTELXXX AGL030YWW UCG81XXXX XXXXXXXX
Country of Origin Date Code Customer Mark (if applicable)
Figure 1 *
Example of Device Marking for Small Form Factor Packages
ProASIC3 nano Product Available in the Z Feature Grade
Devices Packages A3PN030 QN48 QN68 VQ100 A3PN060 - - VQ100 A3PN125 - - VQ100 A3PN250 - - VQ100
Temperature Grade Offerings
ProASIC3 nano Devices ProASIC3 nano-Z Devices QN48 QN68 VQ100 C, I - - - C, I - - C, I - A3PN010 A3PN015 A3PN020 A3PN030Z1 C, I C, I C, I A3PN060 A3PN060Z - - C, I A3PN125 A3PN125Z - - C, I A3PN250 A3PN250Z - - C, I
Notes: 1. A3PN030 is available in the Z feature grade only. 2. C = Commercial temperature range: -20C to 70C ambient temperature 3. I = Industrial temperature range: -40C to 85C ambient temperature
Speed Grade and Temperature Grade Matrix
Temperature Grade C1 I
2
Std.

Notes: 1. C = Commercial temperature range: -20C to 70C ambient temperature. 2. I = Industrial temperature range: -40C to 85C ambient temperature. Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx.
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ProASIC3 nano Flash FPGAs
Table of Contents
ProASIC3 nano Device Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
ProASIC3 nano DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49 Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53 Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59 Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
Package Pin Assignments
48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 68-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
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1 - ProASIC3 nano Device Overview
General Description
ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS(R) family. Nonvolatile flash technology gives ProASIC3 nano devices the advantage of being a secure, low power, single-chip solution that is live at power-up (LAPU). ProASIC3 nano devices are reprogrammable and offer time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. ProASIC3 nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). A3PN030 and smaller devices do not have PLL or RAM support. ProASIC3 nano devices have up to 250,000 system gates, supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os. ProASIC3 nano devices increase the breadth of the ProASIC3 product line by adding new features and packages for greater customer value in high volume consumer, portable, and battery-backed markets. Added features include smaller footprint packages designed with two-layer PCBs in mind, low power, hot-swap capability, and Schmitt trigger for greater flexibility in low-cost and power-sensitive applications.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAMbased FPGAs, flash-based ProASIC3 nano devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3 nano device architecture mitigates the need for ASIC migration at higher user volumes. This makes the ProASIC3 nano device a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/communications, computing, and avionics markets. With a variety of devices under $1, Actel ProASIC3 nano FPGAs enable cost-effective implementation of programmable logic and quick time to market.
Security
Nonvolatile, flash-based ProASIC3 nano devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. ProASIC3 nano devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. ProASIC3 nano devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in ProASIC3 nano devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3 nano devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. ProASIC3 nano devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed ProASIC3 nano device cannot be read back, although secure design verification is possible. Security, built into the FPGA fabric, is an inherent component of ProASIC3 nano devices. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used
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ProASIC3 nano Device Overview to make invasive attacks extremely difficult. ProASIC3 nano devices, with FlashLock and AES security, are unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. A ProASIC3 nano device provides the most impenetrable security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3 nano FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability.
Live at Power-Up
Actel flash-based ProASIC3 nano devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based ProASIC3 nano devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs that are used for these purposes in a system. In addition, glitches and brownouts in system power will not corrupt the ProASIC3 nano device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based ProASIC3 nano devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time.
Firm Errors
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 nano flashbased FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 nano FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based ProASIC3 nano devices exhibit power characteristics similar to an ASIC, making them an ideal choice for power-sensitive applications. ProASIC3 nano devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. ProASIC3 nano devices also have low dynamic power consumption to further maximize power savings.
Advanced Flash Technology
ProASIC3 nano devices offer many benefits, including nonvolatility and reprogrammability through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy.
Advanced Architecture
The proprietary ProASIC3 nano architecture provides granularity comparable to standard-cell ASICs. The ProASIC3 nano device consists of five distinct and programmable architectural features (Figure 1-3 to Figure 1-4 on page 1-4): * FPGA VersaTiles
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ProASIC3 nano Flash FPGAs * * * * Dedicated FlashROM Dedicated SRAM/FIFO memory Extensive CCCs and PLLs Advanced I/O structure
Bank 1*
I/Os
Bank 0 Bank 1
VersaTile
User Nonvolatile FlashROM
Charge Pumps
CCC-GL
Bank 1
Note: *Bank 0 for the A3PN030 device Figure 1-1 * ProASIC3 Device Architecture Overview with Two I/O Banks and No RAM (A3PN010 and A3PN030)
Bank 1
I/Os
Bank 0 Bank 2
VersaTile
User Nonvolatile FlashROM
Charge Pumps
CCC-GL
Bank 1
Figure 1-2 *
ProASIC3 nano Architecture Overview with Three I/O Banks and No RAM (A3PN015 and A3PN020)
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ProASIC3 nano Device Overview
Bank 0
CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block
Bank 1 Bank 0
I/Os
VersaTile
Bank 1 Bank 0 ISP AES Decryption User Nonvolatile FlashROM Bank 1
Charge Pumps
Figure 1-3 *
ProASIC3 nano Device Architecture Overview with Two I/O Banks (A3PN060 and A3PN125)
Bank 0
CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block
Bank 3 Bank 1
I/Os
Bank 3
VersaTile
Bank 1
ISP AES Decryption
User Nonvolatile FlashROM Bank 2
Charge Pumps
Figure 1-4 *
ProASIC3 nano Device Architecture Overview with Four I/O Banks (A3PN250) The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the ProASIC3 nano core tile as either a three-input lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC3 family of third-generation architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design.
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ProASIC3 nano Flash FPGAs In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of ProASIC3 nano devices via an IEEE 1532 JTAG interface.
VersaTiles
The ProASIC3 nano core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS(R) core tiles. The ProASIC3 nano VersaTile supports the following: * * * * All 3-input logic functions--LUT-3 equivalent Latch with clear or set D-flip-flop with clear or set Enable D-flip-flop with clear or set
Refer to Figure 1-5 for VersaTile configurations.
LUT-3 Equivalent X1 X2 X3
D-Flip-Flop with Clear or Set Data CLK CLR Y D-FF
Enable D-Flip-Flop with Clear or Set Data CLK Enable CLR D-FF Y
LUT-3
Y
Figure 1-5 *
VersaTile Configurations
User Nonvolatile FlashROM
Actel ProASIC3 nano devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: * * * * * * * * Internet protocol addressing (wireless or fixed) System calibration settings Device serialization and/or inventory control Subscription-based business models (for example, set-top boxes) Secure key storage for secure communications algorithms Asset management/tracking Date stamping Version management
The FlashROM is written using the standard ProASIC3 nano IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in the A3PN030 and smaller devices), as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Actel ProASIC3 nano development software solutions, Libero(R) Integrated Design Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature enables the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive
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ProASIC3 nano Device Overview programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents.
SRAM and FIFO
ProASIC3 nano devices (except the A3PN030 and smaller devices) have embedded SRAM blocks along their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256x18, 512x9, 1kx4, 2kx2, and 4kx1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in A3PN030 and smaller devices). In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
Higher density ProASIC3 nano devices using either the two I/O bank or four I/O bank architectures provide the designer with very flexible clock conditioning capabilities. A3PN060, A3PN125, and A3PN250 contain six CCCs. One CCC (center west side) has a PLL. The A3PN030 and smaller devices use different CCCs in their architecture. These CCC-GLs contain a global MUX but do not have any PLLs or programmable delays. For devices using the six CCC block architecture, these six CCC blocks are located at the four corners and the centers of the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from dedicated connections to the CCC block, which are located near the CCC. The CCC block has these key features: * * * * * * * * * * * * Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz Clock delay adjustment via programmable and fixed delays from -7.56 ns to +11.12 ns 2 programmable delay types for clock skew minimization Clock frequency synthesis (for PLL only) Internal phase shift = 0, 90, 180, and 270. Output phase shift depends on the output divider configuration (for PLL only). Output duty cycle = 50% 1.5% or better (for PLL only) Low output jitter: worst case < 2.5% x clock period peak-to-peak period jitter when single global network used (for PLL only) Maximum acquisition time = 300 s (for PLL only) Low power consumption of 5 mW Exceptional tolerance to input period jitter--allowable input jitter is up to 1.5 ns (for PLL only) Four precise phases; maximum misalignment between adjacent phases of 40 ps x (350 MHz / fOUT_CCC) (for PLL only)
Additional CCC specifications:
Global Clocking
ProASIC3 nano devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high fanout nets.
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ProASIC3 nano Flash FPGAs
I/Os with Advanced I/O Standards
ProASIC3 nano FPGAs feature a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). The I/Os are organized into banks, with two, three, or four banks per device. The configuration of these banks determines the I/O standards supported. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of various single-data-rate applications for all versions of nano devices and double-datarate applications for the A3PN060, A3PN125, and A3PN250 devices. ProASIC3 nano devices support LVTTL and LVCMOS I/O standards, are hot-swappable, and support cold-sparing and Schmitt trigger. Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system. Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating.
Wide Range I/O Support
Actel nano devices support JEDEC-defined wide range I/O operation. ProASIC3 nano supports the JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components with greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications.
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2 - ProASIC3 nano DC and Switching Characteristics
General Specifications
The Z feature grade does not support the enhanced nano features of Schmitt trigger input, cold-sparing, and hot-swap I/O capability. Refer to the "ProASIC3 nano Ordering Information" section on page III for more information. DC and switching characteristics for -F speed grade targets are based only on simulation. The characteristics provided for the -F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The -F speed grade is only supported in the commercial temperature range.
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 * Absolute Maximum Ratings Symbol VCC VJTAG VPUMP VCCPLL VCCI VI TSTG 1 TJ
1
Parameter DC core supply voltage JTAG DC voltage Programming voltage Analog power supply (PLL) DC I/O output buffer supply voltage I/O input voltage Storage temperature Junction temperature
Limits -0.3 to 1.65 -0.3 to 3.75 -0.3 to 3.75 -0.3 to 1.65 -0.3 to 3.75 -0.3 V to 3.6 V -65 to +150 +125
Units V V V V V V C C
Notes:
1. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2. 2. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.
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ProASIC3 nano DC and Switching Characteristics Table 2-2 * Recommended Operating Conditions 1, 2 Symbol TA TJ VCC
3
Parameter Ambient temperature Junction temperature 1.5 V DC core supply voltage JTAG DC voltage Programming voltage Programming Mode Operation
4 3
Extended Commercial -20 to +70
2
Industrial -40 to +85
2
Units C C V V V V V V V V V V
-20 to +85 1.425 to 1.575 1.4 to 3.6 3.15 to 3.45 0 to 3.6 1.425 to 1.575 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 3.0 to 3.6 2.7 to 3.6
-40 to +100 1.425 to 1.575 1.4 to 3.6 3.15 to 3.45 0 to 3.6 1.425 to 1.575 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 3.0 to 3.6 2.7 to 3.6
VJTAG VPUMP 4
5
VCCPLL
Analog power supply (PLL)
1.5 V DC core supply voltage
VCCI and 1.5 V DC supply voltage VMV 7 1.8 V DC supply voltage 2.5 V DC supply voltage 3.3 V DC supply voltage 3.3 V Wide Range supply voltage 6 Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel recommends that the user follow best design practices using Actel's timing and power simulation tools. 3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-14 on page 2-16. VMV and VCCI should be at the same voltage within a given I/O bank. 4. VPUMP can be left floating during operation (not programming mode). 5. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions and Packaging" chapter for further information. 6. 3.3 V Wide Range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation. 7. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions and Packaging" chapter for further information.
Table 2-3 * Flash Programming Limits - Retention, Storage and Operating Temperature1 Product Grade Commercial Industrial Notes:
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits.
Maximum Operating Programming Program Retention Maximum Storage Cycles (biased/unbiased) Temperature TSTG (C) 2 Junction Temperature TJ (C) 2 500 20 years 110 100 500 20 years 110 100
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ProASIC3 nano Flash FPGAs Table 2-4 * Overshoot and Undershoot Limits 1 VCCI and VMV 2.7 V or less 3V 3.3 V 3.6 V Notes:
1. Based on reliability requirements at 85C. 2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.
Average VCCI-GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle 2 10% 5% 10% 5% 10% 5% 10% 5%
Maximum Overshoot/ Undershoot 2 1.4 V 1.49 V 1.1 V 1.19 V 0.79 V 0.88 V 0.45 V 0.54 V
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every ProASIC(R)3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4. There are five regions to consider during power-up. ProASIC3 I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4). 2. VCCI > VCC - 0.75 V (typical) 3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: * * During programming, I/Os become tristated and weakly pulled up to VCCI. JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior.
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the ProASIC3 nano FPGA Fabric User's Guide for information on clock and lock recovery.
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Internal Power-Up Activation Sequence
1. Core 2. Input buffers 3. Output buffers, after 200 ns delay from input buffer activation
VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V
Region 4: I/O buffers are ON. I/Os are functional but slower because VCCI Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL , VOH / VOL , etc.
Region 1: I/O Buffers are OFF
is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH/VOL levels.
VCC = 1.425 V
Region 2: I/O buffers are ON. I/Os are functional but slower because VCCI / VCC are below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification.
Activation trip point: Va = 0.85 V 0.25 V Deactivation trip point: Vd = 0.75 V 0.25 V
Region 1: I/O buffers are OFF
Activation trip point: Va = 0.9 V 0.3 V Deactivation trip point: Vd = 0.8 V 0.3 V
Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V
VCCI
Figure 2-1 *
I/O State as a Function of VCCI and VCC Voltage Levels
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Thermal Characteristics
Introduction
The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. EQ 1 can be used to calculate junction temperature. TJ = Junction Temperature = T + TA EQ 1 where: TA = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5. P = Power dissipation
Package Thermal Characteristics
The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction temperature is 100C. EQ 2 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air. Max. junction temp. (C) - Max. ambient temp. (C) 100C - 70C * Maximum Power Allowed = ----------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 1.463 W ja (C/W) 20.5C/W EQ 2 Table 2-5 * Package Thermal Resistivities ja Package Type Quad Flat No Lead (QFN) Device All devices Pin Count 48 68 100 Very Thin Quad Flat Pack (VQFP) All devices 100 jc TBD TBD TBD 10.0 Still Air 200 ft./min. TBD TBD TBD 35.3 TBD TBD TBD 29.4 500 ft./min. Units TBD TBD TBD 27.1 C/W C/W C/W C/W
Temperature and Voltage Derating Factors
Table 2-6 * Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70C, VCC = 1.425 V) Junction Temperature (C) Array Voltage VCC (V) 1.425 1.500 1.575 -40C 0.968 0.888 0.836 -20C 0.973 0.894 0.841 0C 0.979 0.899 0.845 25C 0.991 0.910 0.856 70C 1.000 0.919 0.864 85C 1.006 0.924 0.870 100C 1.013 0.930 0.875
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Calculating Power Dissipation
Quiescent Supply Current
Table 2-7 * Quiescent Supply Current Characteristics A3PN010 Typical (25C) Max. (Commercial) Max. (Industrial) 600 A 5 mA 8 mA A3PN015 1 mA 5 mA 8 mA A3PN020 1 mA 5 mA 8 mA A3PN060 2 mA 10 mA 15 mA A3PN125 2 mA 10 mA 15 mA A3PN250 3 mA 20 mA 30 mA
Note: IDD includes VCC, VPUMP, and VCCI, currents.
Power per I/O Pin
Table 2-8 * Summary of I/O Input Buffer Power (Per Pin) - Default I/O Software Settings VCCI (V) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVTTL / 3.3 V LVCMOS - Schmitt Trigger 3.3 V LVCMOS wide range2 3.3 V LVCMOS wide range - Schmitt Trigger 2.5 V LVCMOS 2.5 V LVCMOS - Schmitt Trigger 1.8 V LVCMOS 1.8 V LVCMOS - Schmitt Trigger 1.5 V LVCMOS (JESD8-11) 1.5 V LVCMOS (JESD8-11) - Schmitt Trigger Notes:
1. PAC9 is the total dynamic power measured on VCCI. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
Dynamic Power, PAC9 (W/MHz)1
3.3 3.3 3.3 3.3 2.5 2.5 1.8 1.8 1.5 1.5
16.45 18.93 16.45 18.93 4.73 6.14 1.68 1.80 0.99 0.96
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ProASIC3 nano Flash FPGAs Table 2-9 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings1 CLOAD (pF) 2 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS wide range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. Values for A3PN020, A3PN015, and A3PN010. A3PN060, A3PN125, and A3PN250 correspond to a default loading of 35 pF. 3. PAC10 is the total dynamic power measured on VCCI. 4. All LVCMOS3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
4
VCCI (V)
Dynamic Power, PAC10 (W/MHz)3
10 10 10 10 10
3.3 3.3 2.5 1.8 1.5
162.01 162.01 91.96 46.95 32.22
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Power Consumption of Various Internal Resources
Table 2-10 * Different Components Contributing to Dynamic Power Consumption in ProASIC3 nano Devices Device Specific Dynamic Contributions (W/MHz) A3PN250 A3PN125 A3PN060 A3PN020 A3PN015 A3PN010 9.3 0.4 A3PN010
Parameter PAC1 PAC2 PAC3 PAC4 PAC5 PAC6 PAC7 PAC8 PAC9 PAC10 PAC11 PAC12 PAC13
Definition Clock contribution of a Global Rib Clock contribution of a Global Spine Clock contribution of a VersaTile row Clock contribution of a VersaTile used as a sequential module First contribution of a VersaTile used as a sequential module Second contribution of a VersaTile used as a sequential module Contribution of a VersaTile used as a combinatorial Module Average contribution of a routing net Contribution of an I/O input pin (standard-dependent) Contribution of an I/O output pin (standard-dependent) Average contribution of a RAM block during a read operation Average contribution of a RAM block during a write operation Dynamic contribution for PLL
11.03 1.58
11.03 0.81
9.3 0.81 0.81 0.12 0.07 0.29 0.29 0.70
9.3 0.4
9.3 0.4
See Table 2-8 on page 2-6. See Table 2-9 on page 2-7. 25.00 30.00 2.60 N/A N/A N/A
Note: For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power spreadsheet calculator or SmartPower tool in Libero(R) Integrated Design Environment (IDE) software. Table 2-11 * Different Components Contributing to the Static Power Consumption in ProASIC3 nano Devices Device Specific Static Power (mW) A3PN250 A3PN125 A3PN060 A3PN020 A3PN015 N/A
Parameter PDC1 PDC4 PDC5 Notes:
Definition Array static power in Active mode Static PLL contribution 1
See Table 2-7 on page 2-6. 2.55
Bank quiescent power (VCCI-dependent)
See Table 2-7 on page 2-6.
1. Minimum contribution of the PLL when running at lowest frequency. 2. For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power spreadsheet calculator or SmartPower tool in Libero IDE.
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Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation methodology described below uses the following variables: * * * * * * * * The number of PLLs as well as the number and the frequency of each output clock generated The number of combinatorial and sequential cells used in the design The internal clock frequencies The number and the standard of I/O pins used in the design The number of RAM blocks used in the design Toggle rates of I/O pins as well as VersaTiles--guidelines are provided in Table 2-12 on page 2-11. Enable rates of output buffers--guidelines are provided for typical applications in Table 2-13 on page 2-11. Read rate and write rate to the memory--guidelines are provided for typical applications in Table 2-13 on page 2-11. The calculation should be repeated for each clock domain defined in the design.
Methodology
Total Power Consumption--PTOTAL
PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption.
Total Static Power Consumption--PSTAT
PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design.
Total Dynamic Power Consumption--PDYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution--PCLOCK
PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK NSPINE is the number of global spines used in the user design--guidelines are provided in Table 2-12 on page 2-11. NROW is the number of VersaTile rows used in the design--guidelines are provided in Table 2-12 on page 2-11. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution--PS-CELL
PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1.
1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-12 on page 2-11.
FCLK is the global clock signal frequency.
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Combinatorial Cells Contribution--PC-CELL
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. FCLK is the global clock signal frequency.
1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-12 on page 2-11.
Routing Net Contribution--PNET
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-12 on page 2-11.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution--PINPUTS
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. FCLK is the global clock signal frequency.
2 is the I/O buffer toggle rate--guidelines are provided in Table 2-12 on page 2-11.
I/O Output Buffer Contribution--POUTPUTS
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate--guidelines are provided in Table 2-12 on page 2-11. 1 is the I/O buffer enable rate--guidelines are provided in Table 2-13 on page 2-11.
FCLK is the global clock signal frequency.
RAM Contribution--PMEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
2 is the RAM enable rate for read operations.
3 is the RAM enable rate for write operations--guidelines are provided in Table 2-13 on page 2-11.
PLL Contribution--PPLL
PPLL = PDC4 + PAC13 *FCLKOUT FCLKOUT is the output clock frequency.1
FWRITE-CLOCK is the memory write clock frequency.
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.
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Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: * * The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. The average toggle rate of an 8-bit counter is 25%: - - - - - - Bit 0 (LSB) = 100% Bit 1 Bit 2 ... Bit 7 (MSB) = 0.78125% Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 = 50% = 25%
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-12 * Toggle Rate Guidelines Recommended for Power Calculation Component Definition Toggle rate of VersaTile outputs I/O buffer toggle rate Guideline 10% 10%
1 2
Component
Table 2-13 * Enable Rate Guidelines Recommended for Power Calculation Definition I/O output buffer enable rate RAM enable rate for read operations RAM enable rate for write operations Guideline 100% 12.5% 12.5%
1 2 3
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ProASIC3 nano DC and Switching Characteristics
User I/O Characteristics
Timing Model
I/O Module (Non-Registered) Combinational Cell Y tPD = 0.56 ns Combinational Cell Y tPD = 0.49 ns tDP = 2.25 ns Combinational Cell Y tPD = 0.87 ns Combinational Cell I/O Module (Registered) tPY = 1.04 ns tDP = 2.21 ns Input LVCMOS 2.5 V D Q tPD = 0.51 ns Combinational Cell Y tICLKQ = 0.24 ns tISUD = 0.26 ns Input LVTTL Clock Register Cell tPY = 0.84 ns I/O Module (Non-Registered) tCLKQ = 0.55 ns tSUD = 0.43 ns tPY = 1.14 ns Input LVTTL Clock tPY = 0.84 ns D Q Combinational Cell Y tPD = 0.47 ns tCLKQ = 0.55 ns tSUD = 0.43 ns Input LVTTL Clock tPY = 0.84 ns Register Cell D Q D tPD = 0.47 ns tDP = 3.02 ns I/O Module (Non-Registered) LVCMOS 1.5 V Output drive strength = 2 mA High slew rate Y LVTTL Output drive strength = 8 mA High slew rate tDP = 2.87 ns I/O Module (Non-Registered) I/O Module (Non-Registered) LVTTL Output drive strength = 4 mA High slew rate LVCMOS 2.5V Output Drive Strength = 8 mA High Slew Rate
I/O Module (Registered) Q tDP = 2.21 ns tOCLKQ = 0.59 ns tOSUD = 0.31 ns LVTTL 3.3 V Output drive strength = 8 mA High slew rate
LVCMOS 1.5 V
Figure 2-2 *
Timing Model Operating Conditions: -2 Speed, Commercial Temperature Range (TJ = 70C), Worst Case VCC = 1.425 V, with Default Loading at 10 pF
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tPY
tDIN
PAD
D Y
Q DIN To Array
CLK
tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F))
I/O Interface
VIH
PAD
Vtrip
Vtrip VCC
VIL
50% Y GND tPY (R) tPY (F) VCC 50% DIN GND tDOUT (R)
Figure 2-3 * Input Buffer Timing Model and Delays (example)
50%
50% tDOUT (F)
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tDOUT DQ DOUT D From Array I/O Interface CLK
tDP PAD Std Load tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) tDOUT VCC 50% VCC 50% 50% VOH Vtrip Vtrip VOL tDP (R) tDP (F) (F)
tDOUT (R) 50%
D
0V
DOUT
0V
PAD
Figure 2-4 *
Output Buffer Model and Delays (example)
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tEOUT D E Q tZL, tZH, tHZ, tLZ, tZLS, tZHS
CLK
EOUT D D Q DOUT CLK PAD
I/O Interface
tEOUT = MAX(tEOUT(r), tEOUT(f)) VCC
D VCC E 50% tEOUT (R) 50% EOUT tZL PAD Vtrip VOL 50% tEOUT (F) VCC 50% tHZ 90% VCCI Vtrip 10% VCCI 50% tZH VCCI 50% tLZ
VCC D VCC E 50% tEOUT (R) 50% tZLS PAD Vtrip VOL Vtrip 50% VCC EOUT 50% VOH 50% tZHS tEOUT (F)
Figure 2-5 *
Tristate Output Buffer Timing Model and Delays (example)
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ProASIC3 nano DC and Switching Characteristics
Overview of I/O Performance
Summary of I/O DC Input and Output Levels - Default I/O Software Settings
Table 2-14 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings Equivalent Software Default Drive Drive Strength Slew Min. I/O Standard Strength Option2 Rate V 3.3 V LVTTL/ 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Notes:
1. Currents are measured at 85C junction temperature. 2. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.
VIL
VIH
VOL
VOH
IOL1 IOH1
Max V 0.8
Min. V 2
Max. V 3.6
Max. V 0.4
Min. V 2.4
mA mA 8 8
8 mA
8 mA
High -0.3
100 A
8 mA
High -0.3
0.8
2
3.6
0.2
VCCI - 0.2 100 100 A A 1.7 8 8 4 2
8 mA 4 mA 2 mA
8 mA 4 mA 2 mA
High -0.3
0.7
1.7
3.6
0.7 0.45
High -0.3 0.35 * VCCI 0.65 * VCCI 3.6
VCCI - 0.45 4 2
High -0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI
Table 2-15 * Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial 1 IIL DC I/O Standards 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Notes:
1. 2. 3. 4. Commercial range (-20C < TA < 70C) Industrial range (-40C < TA < 85C) IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges.
3
Industrial 2
4
IIH
IIL
3
IIH 4 A 15 15 15 15 15
A 10 10 10 10 10
A 10 10 10 10 10
A 15 15 15 15 15
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Summary of I/O Timing Characteristics - Default I/O Software Settings
Table 2-16 * Summary of AC Measuring Points Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Table 2-17 * I/O AC Parameter Definitions Parameter tDP tPY tDOUT tEOUT tDIN tHZ tZH tLZ tZL tZHS tZLS Parameter Definition Data to Pad delay through the Output Buffer Pad to Data delay through the Input Buffer Data to Output Buffer delay through the I/O interface Enable to Output Buffer Tristate Control delay through the I/O interface Input Buffer to Data delay through the I/O interface Enable to Pad delay through the Output Buffer--HIGH to Z Enable to Pad delay through the Output Buffer--Z to HIGH Enable to Pad delay through the Output Buffer--LOW to Z Enable to Pad delay through the Output Buffer--Z to LOW Enable to Pad delay through the Output Buffer with delayed enable--Z to HIGH Enable to Pad delay through the Output Buffer with delayed enable--Z to LOW Measuring Trip Point (Vtrip) 1.4 V 1.4 V 1.2 V 0.90 V 0.75 V
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ProASIC3 nano DC and Switching Characteristics Table 2-18 * Summary of I/O Timing Characteristics--Software Default Settings (at 35 pF) STD Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V For A3PN060, A3PN125, and A3PN250 Equivalent Software Default Drive Strength Option1
Capacitive Load (pF)
Drive Strength (mA)
Slew Rate
tDOUT (ns)
tDIN (ns)
tPYS (ns)
tDP (ns)
tE O U T (ns)
tPY (ns)
tZH (ns)
I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Notes:
8
8 mA
High High High High High
35 35 35 35 35
0.60 0.60 0.60 0.60 0.60
4.57 6.78 4.94 6.53 7.86
0.04 1.13 0.04 1.57 0.04 1.43 0.04 1.35 0.04 1.56
1.52 2.18 1.63 1.90 2.14
0.43 0.43 0.43 0.43 0.43
4.64 3.92 2.60 3.14 6.78 5.72 3.72 4.35 4.71 4.94 2.60 2.98 5.53 6.53 2.62 2.89 6.45 7.86 2.66 2.83
100 A 8 mA 8 4 2 8 mA 4 mA 2 mA
1. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Table 2-19 * Summary of I/O Timing Characteristics--Software Default Settings (at 10 pF) STD Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V For A3PN020, A3PN015, and A3PN010 Equivalent Software Default Drive Strength Option1
Capacitive Load (pF)
Drive Strength (mA)
tEO UT (ns)
Slew Rate
tDOUT (ns)
tDIN (ns)
tDP (ns)
tPY (ns)
tPYS (ns)
tZH (ns)
tLZ (ns) 2.60 3.72 2.60 2.62 2.66 tLZ (ns)
I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Notes:
8
8 mA
High High High High High
10 10 10 10 10
0.60 0.60 0.60 0.60 0.60
2.73 3.94 2.76 3.22 3.76
0.04 0.04 0.04 0.04 0.04
1.13 1.57 1.43 1.35 1.56
1.52 2.18 1.63 1.90 2.14
0.43 0.43 0.43 0.43 0.43
2.77 3.94 2.80 3.24 3.74
2.23 3.16 2.60 3.22 3.76
3.14 4.35 2.98 2.89 2.83
100 A 8 mA 8 4 2 8 mA 4 mA 2 mA
1. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
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tHZ (ns)
tZL (ns)
tHZ (ns)
tZL (ns)
ProASIC3 nano Flash FPGAs
Detailed I/O DC Characteristics
Table 2-20 * Input Capacitance Symbol CIN CINCLK Definition Input capacitance Input capacitance on the clock pin Conditions VIN = 0, f = 1.0 MHz VIN = 0, f = 1.0 MHz Min. Max. 8 8 Units pF pF
Table 2-21 * I/O Output Buffer Maximum Resistances 1 Standard 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 100 A 2 mA 4 mA 6 mA 8 mA 1.8 V LVCMOS 1.5 V LVCMOS Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IO H spec
RPULL-DOWN ()2 100 100 50 50
RPULL-UP ()3 300 300 150 150
Same as equivalent software default drive 100 100 50 50 200 100 200 200 200 100 100 225 112 224
2 mA 4 mA 2 mA
Table 2-22 * I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(WEAK PULL-UP)1 () VCCI 3.3 V 3.3 V (wide range I/Os) 2.5 V 1.8 V 1.5 V Notes:
1. R(WEAK PULL-UP-MAX) = (VCCImax - VOHspec) / I(WEAK PULL-UP-MIN) 2. R(WEAK PULLDOWN-MAX) = (VOLspec) / I(WEAK PULLDOWN-MIN)
R(WEAK PULL-DOWN)2 () Min. 10 K 10 K 12 K 17 K 19 K Max. 45 K 45 K 74 K 110 K 140 K
Min. 10 K 10 K 11 K 18 K 19 K
Max. 45 K 45 K 55 K 70 K 90 K
Revision 8
2- 19
ProASIC3 nano DC and Switching Characteristics Table 2-23 * I/O Short Currents IOSH/IOSL Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 4 mA 6 mA 8 mA 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 100 A 2 mA 4 mA 6 mA 8 mA 1.8 V LVCMOS 2 mA 4 mA 1.5 V LVCMOS Note: *TJ = 100C The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 8 mA I/O setting, which is the worst case for this type of analysis. For example, at 100C, the short current condition would have to be sustained for more than six months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-24 * Duration of Short Circuit Event before Failure Temperature -40C -20C 0C 25C 70C 85C 100C Time before Failure > 20 years > 20 years > 20 years > 20 years 5 years 2 years 6 months 2 mA IOSL (mA)* 25 25 51 51 IOSH (mA)* 27 27 54 54
Same as equivalent software default drive 16 16 32 32 9 17 13 18 18 37 37 11 22 16
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ProASIC3 nano Flash FPGAs Table 2-25 * Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers Input Buffer Configuration 3.3 V LVTTL / LVCMOS (Schmitt trigger mode) 2.5 V LVCMOS (Schmitt trigger mode) 1.8 V LVCMOS (Schmitt trigger mode) 1.5 V LVCMOS (Schmitt trigger mode) Table 2-26 * I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer LVTTL/LVCMOS (Schmitt trigger disabled) LVTTL/LVCMOS (Schmitt trigger enabled) Input Rise/Fall Time (min.) No requirement Input Rise/Fall Time (max.) 10 ns * Reliability 20 years (100C) Hysteresis Value (typ.) 240 mV 140 mV 80 mV 60 mV
No requirement
No requirement, but input noise voltage cannot exceed Schmitt hysteresis
20 years (100C)
Note: The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.
Revision 8
2- 21
ProASIC3 nano DC and Switching Characteristics
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor-Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-27 * Minimum and Maximum DC Input and Output Levels 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Software default selection highlighted in gray.
VIL Min. V -0.3 -0.3 -0.3 -0.3 Max. V 0.8 0.8 0.8 0.8 Min. V 2 2 2 2
VIH Max. V 3.6 3.6 3.6 3.6
VOL Max. V 0.4 0.4 0.4 0.4
VOH Min. V 2.4 2.4 2.4 2.4
IOL IOH mA mA 2 4 6 8 2 4 6 8
IOSL Max. mA3 25 25 51 51
IOSH Max. mA3 27 27 54 54
IIL 1 IIH 2 A4 A4 10 10 10 10 10 10 10 10
Test Point Datapath 35 pF
R=1k Test Point Enable Path
R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ
Figure 2-6 *
AC Loading
Table 2-28 * 3.3 V LVTTL/LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Notes:
1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points. 2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.
Input HIGH (V) 3.3
Measuring Point* (V) 1.4
CLOAD (pF) 10
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ProASIC3 nano Flash FPGAs
Timing Characteristics
Table 2-29 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Drive Strength 2 mA Speed Grade Std. -1 -2 4 mA Std. -1 -2 6 mA Std. -1 -2 8 mA Std. -1 -2 tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 tDP 9.70 8.26 7.25 9.70 8.26 7.25 6.90 5.87 5.15 6.90 5.87 5.15 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.13 0.96 0.84 1.13 0.96 0.84 1.13 0.96 0.84 1.13 0.96 0.84 tPYS 1.52 1.29 1.13 1.52 1.29 1.13 1.52 1.29 1.13 1.52 1.29 1.13 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 tZL 9.88 8.40 7.37 9.88 8.40 7.37 7.01 5.97 5.24 7.01 5.97 5.24 tZH 8.82 7.50 6.59 8.82 7.50 6.59 6.22 5.29 4.64 6.22 5.29 4.64 tLZ 2.31 1.96 1.72 2.31 1.96 1.72 2.61 2.22 1.95 2.61 2.22 1.95 tHZ 2.50 2.13 1.87 2.50 2.13 1.87 3.01 2.56 2.25 3.01 2.56 2.25 Units ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-30 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Drive Strength 2 mA Speed Grade Std. -1 -2 4 mA Std. -1 -2 6 mA Std. -1 -2 8 mA Std. -1 -2 Notes:
1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45
tDP 7.19 6.12 5.37 7.19 6.12 5.37 4.57 3.89 3.41 4.57 3.89 3.41
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.13 0.96 0.84 1.13 0.96 0.84 1.13 0.96 0.84 1.13 0.96 0.84
tPYS 1.52 1.29 1.13 1.52 1.29 1.13 1.52 1.29 1.13 1.52 1.29 1.13
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 7.32 6.22 5.46 7.32 6.22 5.46 4.64 3.95 3.47 4.64 3.95 3.47
tZH 6.40 5.44 4.78 6.40 5.44 4.78 3.92 3.33 2.93 3.92 3.33 2.93
tLZ 2.30 1.96 1.72 2.30 1.96 1.72 2.60 2.22 1.95 2.60 2.22 1.95
tHZ 2.62 2.23 1.96 2.62 2.23 1.96 3.14 2.67 2.34 3.14 2.67 2.34
Units ns ns ns ns ns ns ns ns ns ns ns ns
Revision 8
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ProASIC3 nano DC and Switching Characteristics Table 2-31 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010 Drive Strength 2 mA Speed Grade Std. -1 -2 4 mA Std. -1 -2 6 mA Std. -1 -2 8 mA Std. -1 -2 tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 tDP 5.48 4.66 4.09 5.48 4.66 4.09 4.33 3.69 3.24 4.33 3.69 3.24 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.13 0.96 0.84 1.13 0.96 0.84 1.13 0.96 0.84 1.13 0.96 0.84 tPYS 1.52 1.29 1.13 1.52 1.29 1.13 1.52 1.29 1.13 1.52 1.29 1.13 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 tZL 5.58 4.74 4.16 5.58 4.74 4.16 4.40 3.75 3.29 4.40 3.75 3.29 tZH 5.21 4.43 3.89 5.21 4.43 3.89 4.14 3.52 3.09 4.14 3.52 3.09 tLZ 2.31 1.96 1.72 2.31 1.96 1.72 2.61 2.22 1.95 2.61 2.22 1.95 tHZ 2.50 2.13 1.87 2.50 2.13 1.87 3.01 2.56 2.25 3.01 2.56 2.25 Units ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-32 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010 Drive Strength 2 mA Speed Grade Std. -1 -2 4 mA Std. -1 -2 6 mA Std. -1 -2 8 mA Std. -1 -2 Notes:
1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45
tDP 3.56 3.03 2.66 3.56 3.03 2.66 2.73 2.32 2.04 2.73 2.32 2.04
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.13 0.96 0.84 1.13 0.96 0.84 1.13 0.96 0.84 1.13 0.96 0.84
tPYS 1.52 1.29 1.13 1.52 1.29 1.13 1.52 1.29 1.13 1.52 129 1.13
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 3.62 3.08 2.70 3.62 3.08 2.70 2.77 2.36 2.07 2.77 2.36 2.07
tZH 3.03 2.58 2.26 3.03 2.58 2.26 2.23 1.90 1.67 2.23 1.90 1.67
tLZ 2.30 1.96 1.72 2.30 1.96 1.72 2.60 2.22 1.95 2.60 2.22 1.95
tHZ 2.62 2.23 1.96 2.62 2.23 1.96 3.14 2.67 2.34 3.14 2.67 2.34
Units ns ns ns ns ns ns ns ns ns ns ns ns
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ProASIC3 nano Flash FPGAs
3.3 V LVCMOS Wide Range
Table 2-33 * Minimum and Maximum DC Input and Output Levels for 3.3 V LVCMOS Wide Range 3.3 V LVCMOS Wide Range Equivalent Software Default Drive Strength Option3 2 mA 4 mA 6 mA 8 mA VIL VIH VOL VOH IOL IOH IIL 1 IIH 2
Drive Strength 100 A 100 A 100 A 100 A Notes:
Min. V -0.3 -0.3 -0.3 -0.3
Max. V 0.8 0.8 0.8 0.8
Min. V 2 2 2 2
Max. V 3.6 3.6 3.6 3.6
Max. V 0.2 0.2 0.2 0.2
Min. V VDD - 0.2 VDD - 0.2 VDD - 0.2 VDD - 0.2
mA 100 100 100 100
mA 100 100 100 100
A4 10 10 10 10
A4 10 10 10 10
1. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 4. Currents are measured at 85C junction temperature. 5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V Wide Range, as specified in the JESD8-B specification. 6. Software default selection highlighted in gray.
Revision 8
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ProASIC3 nano DC and Switching Characteristics
Timing Characteristics
Table 2-34 * 3.3 V LVCMOS Wide Range Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Equivalent Software Default Drive Drive Strength Speed Grade Strength Option1 100 A 2 mA Std. -1 -2 100 A 4 mA Std. -1 -2 100 A 6 mA Std. -1 -2 100 A 8 mA Std. -1 -2 Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45
tDP 14.73 12.53 11.00 14.73 12.53 11.00 10.38 8.83 7.75 10.38 8.83 7.75
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.57 1.33 1.17 1.57 1.33 1.17 1.57 1.33 1.17 1.57 1.33 1.17
tPYS 2.18 1.85 1.62 2.18 1.85 1.62 2.18 1.85 1.62 2.18 1.85 1.62
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL
tZH
tLZ 3.26 2.77 2.43 3.26 2.77 2.43 3.72 3.17 2.78 3.72 3.17 2.78
tHZ 3.38 2.87 2.52 3.38 2.87 2.52 4.16 3.54 3.11 4.16 3.54 3.11
Units ns ns ns ns ns ns ns ns ns ns ns ns
14.73 13.16 12.53 11.19 11.00 9.83
14.73 13.16 12.53 11.19 11.00 10.38 8.83 7.75 10.38 8.83 7.75 9.83 9.21 7.83 6.88 9.21 7.83 6.88
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ProASIC3 nano Flash FPGAs Table 2-35 * 3.3 V LVCMOS Wide Range High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Equivalent Software Default Drive Drive Strength Speed Grade Strength Option1 100 A 2 mA Std. -1 -2 100 A 4 mA Std. -1 -2 100 A 6 mA Std. -1 -2 100 A 8 mA Std. -1 -2 Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 3. Software default selection highlighted in gray.
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45
tDP 10.83 9.22 8.09 10.83 9.22 8.09 6.78 5.77 5.06 6.78 5.77 5.06
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.57 1.33 1.17 1.57 1.33 1.17 1.57 1.33 1.17 1.57 1.33 1.17
tPYS 2.18 1.85 1.62 2.18 1.85 1.62 2.18 1.85 1.62 2.18 1.85 1.62
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 10.83 9.22 8.09 10.83 9.22 8.09 6.78 5.77 5.06 6.78 5.77 5.06
tZH 9.48 8.06 7.08 9.48 8.06 7.08 5.72 4.87 4.27 5.72 4.87 4.27
tLZ 3.25 2.77 2.43 3.25 2.77 2.43 3.72 3.16 2.78 3.72 3.16 2.78
tHZ 3.56 3.03 2.66 3.56 3.03 2.66 4.35 3.70 3.25 4.35 3.70 3.25
Units ns ns ns ns ns ns ns ns ns ns ns ns
Revision 8
2- 27
ProASIC3 nano DC and Switching Characteristics Table 2-36 * 3.3 V LVCMOS Wide Range Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Software Default Load at 35 pF for A3PN020, A3PN015, A3PN010 Equivalent Software Default Drive Drive Strength Speed Grade Strength Option1 100 A 2 mA Std. -1 -2 100 A 4 mA Std. -1 -2 100 A 6 mA Std. -1 -2 100 A 8 mA Std. -1 -2 Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45
tDP 8.20 6.97 6.12 8.20 6.97 6.12 6.42 5.46 4.79 6.42 5.46 4.79
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.57 1.33 1.17 1.57 1.33 1.17 1.57 1.33 1.17 1.57 1.33 1.17
tPYS 2.18 1.85 1.62 2.18 1.85 1.62 2.18 1.85 1.62 2.18 1.85 1.62
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 8.20 6.97 6.12 8.20 6.97 6.12 6.42 5.46 4.79 6.42 5.46 4.79
tZH 7.68 6.53 5.73 7.68 6.53 5.73 6.05 5.14 4.52 6.05 5.14 4.52
tLZ 3.26 2.77 2.43 3.26 2.77 2.43 3.72 3.17 2.78 3.72 3.17 2.78
tHZ 3.38 2.87 2.52 3.38 2.87 2.52 4.16 3.54 3.11 4.16 3.54 3.11
Units ns ns ns ns ns ns ns ns ns ns ns ns
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ProASIC3 nano Flash FPGAs Table 2-37 * 3.3 V LVCMOS Wide Range High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Software Default Load at 35 pF for A3PN020, A3PN015, A3PN010 Equivalent Software Default Drive Drive Strength Speed Grade Strength Option1 100 A 2 mA Std. -1 -2 100 A 4 mA Std. -1 -2 100 A 6 mA Std. -1 -2 100 A 8 mA Std. -1 -2 Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 3. Software default selection highlighted in gray.
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45
tDP 5.23 4.45 3.90 5.23 4.45 3.90 3.94 3.35 2.94 3.94 3.35 2.94
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.57 1.33 1.17 1.57 1.33 1.17 1.57 1.33 1.17 1.57 1.33 1.17
tPYS 2.18 1.85 1.62 2.18 1.85 1.62 2.18 1.85 1.62 2.18 1.85 1.62
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 5.23 4.45 3.90 5.23 4.45 3.90 3.94 3.35 2.94 3.94 3.35 2.94
tZH 4.37 3.71 3.26 4.37 3.71 3.26 3.16 2.69 2.36 3.16 2.69 2.36
tLZ 3.25 2.77 2.43 3.25 2.77 2.43 3.72 3.16 2.78 3.72 3.16 2.78
tHZ 3.56 3.03 2.66 3.56 3.03 2.66 4.35 3.70 3.25 4.35 3.70 3.25
Units ns ns ns ns ns ns ns ns ns ns ns ns
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ProASIC3 nano DC and Switching Characteristics
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications. Table 2-38 * Minimum and Maximum DC Input and Output Levels 2.5 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Software default selection highlighted in gray.
VIL Min. V -0.3 -0.3 -0.3 -0.3 Max. V 0.7 0.7 0.7 0.7 Min. V 1.7 1.7 1.7 1.7
VIH Max. V 3.6 3.6 3.6 3.6
VOL Max. V 0.7 0.7 0.7 0.7
VOH Min. V 1.7 1.7 1.7 1.7
IOL IOH mA mA 2 4 6 8 2 4 6 8
IOSL Max. mA3 16 16 32 32
IOSH Max. mA3 18 18 37 37
IIL 1 IIH 2 A4 A4 10 10 10 10 10 10 10 10
Test Point Datapath 35 pF
R=1k Test Point Enable Path
R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ
Figure 2-7 *
AC Loading
Table 2-39 * 2.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Notes:
1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points. 2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.
Input HIGH (V) 2.5
Measuring Point* (V) 1.2
CLOAD (pF) 10
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ProASIC3 nano Flash FPGAs
Timing Characteristics
Table 2-40 * 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Drive Strength 2 mA Speed Grade Std. -1 -2 4 mA Std. -1 -2 6 mA Std. -1 -2 8 mA Std. -1 -2 tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 tDP 11.29 9.61 8.43 11.29 9.61 8.43 7.73 6.57 5.77 7.73 6.57 5.77 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.43 1.22 1.07 1.43 1.22 1.07 1.43 1.22 1.07 1.43 1.22 1.07 tPYS 1.63 1.39 1.22 1.63 1.39 1.22 1.63 1.39 1.22 1.63 1.39 1.22 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 tZL 10.64 9.05 7.94 10.64 9.05 7.94 7.70 6.55 5.75 7.70 6.55 5.75 tZH 11.29 9.61 8.43 11.29 9.61 8.43 7.73 6.57 5.77 7.73 6.57 5.77 tLZ 2.27 1.93 1.70 2.27 1.93 1.70 2.60 2.21 1.94 2.60 2.21 1.94 tHZ 2.29 1.95 1.71 2.29 1.95 1.71 2.89 2.46 2.16 2.89 2.46 2.16 Units ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-41 * 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Drive Strength 2 mA Speed Grade Std. -1 -2 4 mA Std. -1 -2 6 mA Std. -1 -2 8 mA Std. -1 -2 Notes:
1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45
tDP 8.38 7.13 6.26 8.38 7.13 6.26 4.94 4.20 3.69 4.94 4.20 3.69
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.43 1.22 1.07 1.43 1.22 1.07 1.43 1.22 1.07 1.43 1.22 1.07
tPYS 1.63 1.39 1.22 1.63 1.39 1.22 1.63 1.39 1.22 1.63 1.39 1.22
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 7.36 6.26 5.50 7.36 6.26 5.50 4.71 4.01 3.52 4.71 4.01 3.52
tZH 8.38 7.13 6.26 8.38 7.13 6.26 4.94 4.20 3.69 4.94 4.20 3.69
tLZ 2.27 1.93 1.69 2.27 1.93 1.69 2.60 2.21 1.94 2.60 2.21 1.94
tHZ 2.37 2.02 1.77 2.37 2.02 1.77 2.98 2.54 2.23 2.98 2.54 2.23
Units ns ns ns ns ns ns ns ns ns ns ns ns
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ProASIC3 nano DC and Switching Characteristics Table 2-42 * 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010 Drive Strength 2 mA Speed Grade Std. -1 -2 4 mA Std. -1 -2 6 mA Std. -1 -2 8 mA Std. -1 -2 tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 tDP 6.40 5.45 4.78 6.40 5.45 4.78 5.00 4.26 3.74 5.00 4.26 3.74 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.43 1.22 1.07 1.43 1.22 1.07 1.43 1.22 1.07 1.43 1.22 1.07 tPYS 1.63 1.39 1.22 1.63 1.39 1.22 1.63 1.39 1.22 1.63 1.39 1.22 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 tZL 6.16 5.24 4.60 6.16 5.24 4.60 4.90 4.17 3.66 4.90 4.17 3.66 tZH 6.40 5.45 4.78 6.40 5.45 4.78 5.00 4.26 3.74 5.00 4.26 3.74 tLZ 2.27 1.93 1.70 2.27 1.93 1.70 2.60 2.21 1.94 2.60 2.21 1.94 tHZ 2.29 1.95 1.71 2.29 1.95 1.71 2.89 2.46 2.16 2.89 2.46 2.16 Units ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-43 * 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010 Drive Strength 2 mA Speed Grade Std. -1 -2 4 mA Std. -1 -2 6 mA Std. -1 -2 8 mA Std. -1 -2 Notes:
1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45 0.60 0.51 0.45
tDP 3.70 3.15 2.77 3.70 3.15 2.77 2.76 2.35 2.06 2.76 2.35 2.06
tDIN 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.43 1.22 1.07 1.43 1.22 1.07 1.43 1.22 1.07 1.43 1.22 1.07
tPYS 1.63 1.39 1.22 1.63 1.39 1.22 1.63 1.39 1.22 1.63 1.39 1.22
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32 0.43 0.36 0.32
tZL 3.66 3.12 2.74 3.66 3.12 2.74 2.80 2.38 2.09 2.80 2.38 2.09
tZH 3.70 3.15 2.77 3.70 3.15 2.77 2.60 2.21 1.94 2.60 2.21 1.94
tLZ 2.27 1.93 1.69 2.27 1.93 1.69 2.60 2.21 1.94 2.60 2.21 1.94
tHZ 2.37 2.02 1.77 2.37 2.02 1.77 2.98 2.54 2.23 2.98 2.54 2.23
Units ns ns ns ns ns ns ns ns ns ns ns ns
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ProASIC3 nano Flash FPGAs
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-44 * Minimum and Maximum DC Input and Output Levels 1.8 V LVCMOS Drive Strength 2 mA 4 mA Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Software default selection highlighted in gray.
VIL Min. V Max. V Min. V
VIH Max. V 3.6 3.6
VOL Max. V 0.45 0.45
VOH Min. V VCCI - 0.45 VCCI - 0.45
IOL IOH mA mA 2 4 2 4
IOSL Max. mA3 9 17
IOSH IIL 1 IIH 2 Max. mA3 A4 A4 11 22 10 10 10 10
-0.3 0.35 * VCCI 0.65 * VCCI -0.3 0.35 * VCCI 0.65 * VCCI
Test Point Datapath 35 pF
R=1k Test Point Enable Path
R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ
Figure 2-8 *
AC Loading
Table 2-45 * 1.8 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Notes:
1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points. 2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.
Input HIGH (V) 1.8
Measuring Point* (V) 0.9
CLOAD (pF) 10
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ProASIC3 nano DC and Switching Characteristics
Timing Characteristics
Table 2-46 * 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Drive Strength 2 mA Speed Grade Std. -1 -2 4 mA Std. -1 -2 tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 tDP 15.36 13.07 11.47 10.32 8.78 7.71 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.35 1.15 1.01 1.35 1.15 1.01 tPYS 1.90 1.61 1.42 1.90 1.61 1.42 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 tZL 13.46 11.45 10.05 9.92 8.44 7.41 tZH 15.36 13.07 11.47 10.32 8.78 7.71 tLZ 2.23 1.90 1.67 2.63 2.23 1.96 tHZ 1.78 1.51 1.33 2.78 2.37 2.08 Units ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-47 * 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Drive Strength 2 mA Speed Grade Std. -1 -2 4 mA Std. -1 -2 Notes:
1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45
tDP 11.42 9.71 8.53 6.53 5.56 4.88
tDIN 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.35 1.15 1.01 1.35 1.15 1.01
tPYS 1.90 1.61 1.42 1.90 1.61 1.42
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32
tZL 8.65 7.36 6.46 5.53 4.70 4.13
tZH 11.42 9.71 8.53 6.53 5.56 4.88
tLZ 2.23 1.89 1.66 2.62 2.23 1.96
tHZ 1.84 1.57 1.37 2.89 2.45 2.15
Units ns ns ns ns ns ns
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R e visio n 8
ProASIC3 nano Flash FPGAs Table 2-48 * 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010 Drive Strength 2 mA Speed Grade Std. -1 -2 4 mA Std. -1 -2 tDOUT 0.60 0.51 0.45 0.60 0.51 0.45 tDP 8.52 7.25 6.36 6.59 5.60 4.92 tDIN 0.04 0.04 0.03 0.04 0.04 0.03 tPY 1.35 1.15 1.01 1.35 1.15 1.01 tPYS 1.90 1.61 1.42 1.90 1.61 1.42 tEOUT 0.43 0.36 0.32 0.43 0.36 0.32 tZL 7.99 6.80 5.97 6.44 5.48 4.81 tZH 8.52 7.25 6.36 6.59 5.60 4.92 tLZ 2.23 1.90 1.67 2.63 2.23 1.96 tHZ 1.78 1.51 1.33 2.78 2.37 2.08 Units ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-49 * 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010 Drive Strength 2 mA Speed Grade Std. -1 -2 4 mA Std. -1 -2 Notes:
1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
tDOUT 0.60 0.51 0.45 0.60 0.51 0.45
tDP 4.79 4.08 3.58 3.22 2.74 2.40
tDIN 0.04 0.04 0.03 0.04 0.04 0.03
tPY 1.35 1.15 1.01 1.35 1.15 1.01
tPYS 1.90 1.61 1.42 1.90 1.61 1.42
tEOUT 0.43 0.36 0.32 0.43 0.36 0.32
tZL 4.27 3.63 3.19 3.24 2.75 2.42
tZH 4.79 4.08 3.58 3.22 2.74 2.40
tLZ 2.23 1.89 1.66 2.62 2.23 1.95
tHZ 1.84 1.57 1.37 2.89 2.45 2.15
Units ns ns ns ns ns ns
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ProASIC3 nano DC and Switching Characteristics
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-50 * Minimum and Maximum DC Input and Output Levels 1.5 V LVCMOS Drive Strength 2 mA Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Software default selection highlighted in gray.
VIL Min. V Max. V
VIH Min. V 0.65 * VCCI Max. V 3.6
VOL Max. V
VOH Min. V
IOL IOH mA mA 2 2
IOSL Max. mA3 13
IOSH
IIL 1 IIH 2
Max. mA3 A4 A4 16 10 10
-0.3 0.35 * VCCI
0.25 * VCCI 0.75 * VCCI
Test Point Datapath 35 pF
R=1k Test Point Enable Path
R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ
Figure 2-9 *
AC Loading
Table 2-51 * 1.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Notes:
1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points. 2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.
Input HIGH (V) 1.5
Measuring Point* (V) 0.75
CLOAD (pF) 10
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ProASIC3 nano Flash FPGAs
Timing Characteristics
Table 2-52 * 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Drive Strength 2 mA Speed Grade Std. -1 -2 tDOUT 0.60 0.51 0.45 tDP 12.58 10.70 9.39 tDIN 0.04 0.04 0.03 tPY 1.56 1.32 1.16 tPYS 2.14 1.82 1.59 tEOUT 0.43 0.36 0.32 tZL 12.18 10.36 9.09 tZH 12.58 10.70 9.39 tLZ 2.67 2.27 1.99 tHZ 2.71 2.31 2.03 Units ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-53 * 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Drive Strength 2 mA Speed Grade Std. -1 -2 Notes:
1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
tDOUT 0.60 0.51 0.45
tDP 7.86 6.68 5.87
tDIN 0.04 0.04 0.03
tPY 1.56 1.32 1.16
tPYS 2.14 1.82 1.59
tEOUT 0.43 0.36 0.32
tZL 6.45 5.49 4.82
tZH 7.86 6.68 5.87
tLZ 2.66 2.26 1.99
tHZ 2.83 2.41 2.12
Units ns ns ns
Table 2-54 * 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010 Drive Strength 2 mA Speed Grade Std. -1 -2 tDOUT 0.60 0.51 0.45 tDP 8.01 6.81 5.98 tDIN 0.04 0.04 0.03 tPY 1.56 1.32 1.16 tPYS 2.14 1.82 1.58 tEOUT 0.43 0.36 0.32 tZL 8.03 6.83 6.00 tZH 8.01 6.81 5.98 tLZ 2.67 2.27 2.10 tHZ 2.71 2.31 2.03 Units ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-55 * 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010 Drive Strength 2 mA Speed Grade Std. -1 -2 Notes:
1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
tDOUT 0.60 0.51 0.45
tDP 3.76 3.20 2.81
tDIN 0.04 0.04 0.03
tPY 1.52 1.32 1.16
tPYS 2.14 1.82 1.59
tEOUT 0.43 0.36 0.32
tZL 3.74 3.18 2.79
tZH 3.76 3.20 2.81
tLZ 2.66 2.26 1.99
tHZ 2.83 2.41 2.12
Units ns ns ns
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ProASIC3 nano DC and Switching Characteristics
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
INBUF
Preset
L
Pad Out
D DOUT Data_out
TRIBUF
Data
PRE D Q C DFN1E1P1 E B
E
Y Core Array
F G
PRE D Q DFN1E1P1 E
INBUF INBUF
Enable
EOUT H I
CLKBUF
CLK
A J K Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered PRE D Q DFN1E1P1 E
CLKBUF
INBUF
INBUF
Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive-Edge Triggered
CLK
Figure 2-10 * Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
2- 38
R e visio n 8
D_Enable
Enable
ProASIC3 nano Flash FPGAs Table 2-56 * Parameter Definition and Measuring Nodes Parameter Name tOCLKQ tOSUD tOHD tOSUE tOHE tOPRE2Q tOREMPRE tORECPRE tOECLKQ tOESUD tOEHD tOESUE tOEHE tOEPRE2Q tOEREMPRE tOERECPRE tICLKQ tISUD tIHD tISUE tIHE tIPRE2Q tIREMPRE tIRECPRE Parameter Definition Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Measuring Nodes (from, to)* H, DOUT F, H F, H G, H G, H L, DOUT L, H L, H H, EOUT J, H J, H K, H K, H I, EOUT I, H I, H A, E C, A C, A B, A B, A D, E D, A D, A
* See Figure 2-10 on page 2-38 for more information.
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ProASIC3 nano DC and Switching Characteristics
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Pad Out
DOUT Y D CC Q EE
DFN1E1C1
Data
Core Array
Data_out FF
TRIBUF
INBUF INBUF
D
Q
DFN1E1C1
GG E BB CLR LL
CLKBUF
E CLR
EOUT
Enable
CLK
HH AA JJ DD KK Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered
INBUF
CLR
D
Q
DFN1E1C1
E CLR
INBUF
INBUF
CLKBUF
Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive-Edge Triggered
Figure 2-11 * Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
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R e visio n 8
D_Enable
Enable
CLK
ProASIC3 nano Flash FPGAs Table 2-57 * Parameter Definition and Measuring Nodes Parameter Name tOCLKQ tOSUD tOHD tOSUE tOHE tOCLR2Q tOREMCLR tORECCLR tOECLKQ tOESUD tOEHD tOESUE tOEHE tOECLR2Q tOEREMCLR tOERECCLR tICLKQ tISUD tIHD tISUE tIHE tICLR2Q tIREMCLR tIRECCLR Parameter Definition Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Measuring Nodes (from, to)* HH, DOUT FF, HH FF, HH GG, HH GG, HH LL, DOUT LL, HH LL, HH HH, EOUT JJ, HH JJ, HH KK, HH KK, HH II, EOUT II, HH II, HH AA, EE CC, AA CC, AA BB, AA BB, AA DD, EE DD, AA DD, AA
* See Figure 2-11 on page 2-40 for more information.
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ProASIC3 nano DC and Switching Characteristics
Input Register
tICKMPWH tICKMPWL 50% 50% tISUD Data 1 50% 0 tIHD 50% 50% 50% 50% 50% 50%
CLK
Enable
50% tIHE 50%
tIWPRE tISUE
tIRECPRE 50% tIWCLR tIRECCLR 50%
tIREMPRE 50% tIREMCLR 50%
Preset
Clear tIPRE2Q Out_1 50% tICLKQ 50%
50%
tICLR2Q
50%
Figure 2-12 * Input Register Timing Diagram
Timing Characteristics
Table 2-58 * Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tICLKQ tISUD tIHD tICLR2Q tIPRE2Q tIREMCLR tIRECCLR tIREMPRE tIRECPRE tIWCLR tIWPRE tICKMPWH tICKMPWL Description Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Asynchronous Clear Minimum Pulse Width for the Input Data Register Asynchronous Preset Minimum Pulse Width for the Input Data Register Clock Minimum Pulse Width HIGH for the Input Data Register Clock Minimum Pulse Width LOW for the Input Data Register -2 -1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns 0.24 0.27 0.32 0.26 0.30 0.35 0.00 0.00 0.00 0.45 0.52 0.61 0.45 0.52 0.61 0.00 0.00 0.00 0.22 0.25 0.30 0.00 0.00 0.00 0.22 0.25 0.30 0.22 0.25 0.30 0.22 0.25 0.30 0.36 0.41 0.48 0.32 0.37 0.43
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
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ProASIC3 nano Flash FPGAs
Output Register
tOCKMPWH tOCKMPWL 50% 50% tOSUD tOHD Data_out 1 50% 0 50% 50% 50% 50% 50% 50%
CLK
Enable
50% tOHE 50%
tOWPRE
tORECPRE 50%
tOREMPRE 50% tOREMCLR 50%
Preset
tOSUE
tOWCLR Clear tOPRE2Q DOUT 50% tOCLKQ 50% tOCLR2Q 50% 50%
tORECCLR
50%
Figure 2-13 * Output Register Timing Diagram
Timing Characteristics
Table 2-59 * Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tOCLKQ tOSUD tOHD tOCLR2Q tOPRE2Q tOREMCLR tORECCLR tOREMPRE tORECPRE tOWCLR tOWPRE tOCKMPWH tOCKMPWL Description Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Asynchronous Clear Minimum Pulse Width for the Output Data Register Asynchronous Preset Minimum Pulse Width for the Output Data Register Clock Minimum Pulse Width HIGH for the Output Data Register Clock Minimum Pulse Width LOW for the Output Data Register -2 -1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns 0.59 0.67 0.79 0.31 0.36 0.42 0.00 0.00 0.00 0.80 0.91 1.07 0.80 0.91 1.07 0.00 0.00 0.00 0.22 0.25 0.30 0.00 0.00 0.00 0.22 0.25 0.30 0.22 0.25 0.30 0.22 0.25 0.30 0.36 0.41 0.48 0.32 0.37 0.43
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
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ProASIC3 nano DC and Switching Characteristics
Output Enable Register
tOECKMPWH tOECKMPWL
50% CLK
50% tOESUD tOEHD
50%
50%
50%
50%
50%
D_Enable
1
50%
0 50%
Enable
50%
tOEWPRE 50%
tOERECPRE 50%
tOEREMPRE 50%
Preset
tOESUEOEHE t
tOEWCLR 50% Clear tOEPRE2Q 50% EOUT tOECLKQ 50% tOECLR2Q 50%
tOERECCLR 50%
tOEREMCLR 50%
Figure 2-14 * Output Enable Register Timing Diagram
Timing Characteristics
Table 2-60 * Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tOECLKQ tOESUD tOEHD tOECLR2Q tOEPRE2Q tOERECCLR tOERECPRE tOEWCLR tOEWPRE Description Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register -2 -1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns 0.44 0.51 0.59 0.31 0.36 0.42 0.00 0.00 0.00 0.67 0.76 0.89 0.67 0.76 0.89 0.00 0.00 0.00 0.22 0.25 0.30 0.00 0.00 0.00 0.22 0.25 0.30 0.22 0.25 0.30 0.22 0.25 0.30 0.36 0.41 0.48 0.32 0.37 0.43
tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Asynchronous Clear Minimum Pulse Width for the Output Enable Register Asynchronous Preset Minimum Pulse Width for the Output Enable Register
tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
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ProASIC3 nano Flash FPGAs
DDR Module Specifications
Input DDR Module
Input DDR
INBUF Data
A FF1
D
Out_QF (to core)
B CLK CLKBUF FF2
E
Out_QR (to core)
CLR INBUF
C
DDR_IN
Figure 2-15 * Input DDR Timing Model Table 2-61 * Parameter Definitions Parameter Name tDDRICLKQ1 tDDRICLKQ2 tDDRISUD tDDRIHD tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR Parameter Definition Clock-to-Out Out_QR Clock-to-Out Out_QF Data Setup Time of DDR input Data Hold Time of DDR input Clear-to-Out Out_QR Clear-to-Out Out_QF Clear Removal Clear Recovery Measuring Nodes (from, to) B, D B, E A, B A, B C, D C, E C, B C, B
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CLK tDDRISUD Data 1 2 3 4 5 6 7 tDDRIHD 8 tDDRIRECCLR CLR tDDRIREMCLR tDDRICLKQ1 tDDRICLR2Q1 Out_QF tDDRICLR2Q2 Out_QR 3 2 4 tDDRICLKQ2 5 7 6 9
Figure 2-16 * Input DDR Timing Diagram
Timing Characteristics
Table 2-62 * Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V Parameter tDDRICLKQ1 tDDRICLKQ2 tDDRISUD Description Clock-to-Out Out_QR for Input DDR Clock-to-Out Out_QF for Input DDR Data Setup for Input DDR (Fall) Data Setup for Input DDR (Rise) tDDRIHD Data Hold for Input DDR (Fall) Data Hold for Input DDR (Rise) tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR tDDRIWCLR tDDRICKMPWH tDDRICKMPWL FDDRIMAX Asynchronous Clear-to-Out Out_QR for Input DDR Asynchronous Clear-to-Out Out_QF for Input DDR Asynchronous Clear Removal time for Input DDR Asynchronous Clear Recovery time for Input DDR Asynchronous Clear Minimum Pulse Width for Input DDR Clock Minimum Pulse Width High for Input DDR Clock Minimum Pulse Width Low for Input DDR Maximum Frequency for Input DDR -2 0.27 0.39 0.28 0.25 0.00 0.00 0.46 0.57 0.00 0.22 0.22 0.36 0.32 350.00 -1 0.31 0.44 0.32 0.28 0.00 0.00 0.53 0.65 0.00 0.25 0.25 0.41 0.37 350.00 Std. 0.37 0.52 0.38 0.33 0.00 0.00 0.62 0.76 0.00 0.30 0.30 0.48 0.43 350.00 Units ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.
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ProASIC3 nano Flash FPGAs
Output DDR Module
Output DDR
Data_F (from core)
A X FF1 B Out X CLKBUF C X D X FF2 1 0 E X OUTBUF
CLK
Data_R (from core)
CLR INBUF
B X C X DDR_OUT
Figure 2-17 * Output DDR Timing Model Table 2-63 * Parameter Definitions Parameter Name tDDROCLKQ tDDROCLR2Q tDDROREMCLR tDDRORECCLR tDDROSUD1 tDDROSUD2 tDDROHD1 tDDROHD2 Clock-to-Out Asynchronous Clear-to-Out Clear Removal Clear Recovery Data Setup Data_F Data Setup Data_R Data Hold Data_F Data Hold Data_R Parameter Definition Measuring Nodes (from, to) B, E C, E C, B C, B A, B D, B A, B D, B
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CLK tDDROSUD2 tDDROHD2 Data_F 1 2 tDDROREMCLR Data_R 6 7 tDDROHD1 8 9 10 tDDRORECCLR CLR tDDROREMCLR tDDROCLR2Q Out tDDROCLKQ 7 2 8 3 9 4 10 11 3 4 5
Figure 2-18 * Output DDR Timing Diagram
Timing Characteristics
Table 2-64 * Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tDDROCLKQ tDDROSUD1 tDDROSUD2 tDDROHD1 tDDROHD2 tDDROCLR2Q tDDROREMCLR tDDRORECCLR tDDROWCLR1 tDDROCKMPWH tDDROCKMPWL FDDOMAX Description Clock-to-Out of DDR for Output DDR Data_F Data Setup for Output DDR Data_R Data Setup for Output DDR Data_F Data Hold for Output DDR Data_R Data Hold for Output DDR Asynchronous Clear-to-Out for Output DDR Asynchronous Clear Removal Time for Output DDR Asynchronous Clear Recovery Time for Output DDR Asynchronous Clear Minimum Pulse Width for Output DDR Clock Minimum Pulse Width HIGH for the Output DDR Clock Minimum Pulse Width LOW for the Output DDR Maximum Frequency for the Output DDR -2 0.70 0.38 0.38 0.00 0.00 0.80 0.00 0.22 0.22 0.36 0.32 -1 0.80 0.43 0.43 0.00 0.00 0.91 0.00 0.25 0.25 0.41 0.37 Std. 0.94 0.51 0.51 0.00 0.00 1.07 0.00 0.30 0.30 0.48 0.43 Units ns ns ns ns ns ns ns ns ns ns ns MHz
350.00 350.00 350.00
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
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ProASIC3 nano Flash FPGAs
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO(R)/e, and ProASIC3/E Macro Library Guide.
A
INV
Y
A OR2 B A AND2 B Y Y
A NOR2 B Y
A NAND2 B A B C Y
A B XOR2 Y
XOR3
Y
A A B C B C
MAJ3 Y
A 0 MUX2 B 1 Y
NAND3
S
Figure 2-19 * Sample of Combinatorial Cells
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tPD
A NAND2 or Any Combinatorial Logic Y
B
tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for the particular combinatorial cell VCC
50% A, B, C
50% GND VCC
50% OUT GND VCC OUT 50% tPD (RF)
Figure 2-20 * Timing Model and Waveforms
50%
tPD (RR)
tPD (FF) tPD (FR) GND 50%
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ProASIC3 nano Flash FPGAs
Timing Characteristics
Table 2-65 * Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Equation Y = !A Y=A*B Y = !(A * B) Y=A+B Y = !(A + B) Y=AB Y = MAJ(A, B, C) Y=ABC Y = A !S + B S Y=A*B*C Parameter tPD tPD tPD tPD tPD tPD tPD tPD tPD tPD -2 0.40 0.47 0.47 0.49 0.49 0.74 0.70 0.87 0.51 0.56 -1 0.46 0.54 0.54 0.55 0.55 0.84 0.79 1.00 0.58 0.64 Std. 0.54 0.63 0.63 0.65 0.65 0.99 0.93 1.17 0.68 0.75 Units ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
VersaTile Specifications as a Sequential Module
The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide.
Data
D DFN1
Q
Out
Data D En CLK Q
Out
DFN1E1
CLK
PRE
Data
D
Q DFN1C1
Out
Data En CLK
D
Q
Out
DFI1E1P1
CLK CLR
Figure 2-21 * Sample of Sequential Cells
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ProASIC3 nano DC and Switching Characteristics
tCKMPWH tCKMPWL 50% tSUD Data 50% tHD 0 50% 50% 50% 50% 50% 50%
CLK
50%
EN 50% tHE PRE tSUE 50% tWPRE tRECPRE 50% tREMPRE 50% tREMCLR 50%
tWCLR CLR tPRE2Q Out tCLKQ 50% 50% 50%
tRECCLR 50%
tCLR2Q 50%
Figure 2-22 * Timing Model and Waveforms
Timing Characteristics
Table 2-66 * Register Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tCLKQ tSUD tHD tSUE tHE tCLR2Q tPRE2Q tREMCLR tRECCLR tREMPRE tRECPRE tWCLR tWPRE tCKMPWH tCKMPWL Description Clock-to-Q of the Core Register Data Setup Time for the Core Register Data Hold Time for the Core Register Enable Setup Time for the Core Register Enable Hold Time for the Core Register Asynchronous Clear-to-Q of the Core Register Asynchronous Preset-to-Q of the Core Register Asynchronous Clear Removal Time for the Core Register Asynchronous Clear Recovery Time for the Core Register Asynchronous Preset Removal Time for the Core Register Asynchronous Preset Recovery Time for the Core Register Asynchronous Clear Minimum Pulse Width for the Core Register Asynchronous Preset Minimum Pulse Width for the Core Register Clock Minimum Pulse Width HIGH for the Core Register Clock Minimum Pulse Width LOW for the Core Register -2 -1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
0.55 0.63 0.74 0.43 0.49 0.57 0.00 0.00 0.00 0.45 0.52 0.61 0.00 0.00 0.00 0.40 0.45 0.53 0.40 0.45 0.53 0.00 0.00 0.00 0.22 0.25 0.30 0.00 0.00 0.00 0.22 0.25 0.30 0.22 0.25 0.30 0.22 0.25 0.30 0.36 0.41 0.48 0.32 0.37 0.43
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
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ProASIC3 nano Flash FPGAs
Global Resource Characteristics
A3PN250 Clock Tree Topology
Clock delays are device-specific. Figure 2-23 is an example of a global tree used for clock routing. The global tree presented in Figure 2-23 is driven by a CCC located on the west side of the A3PN250 device. It is used to drive all D-flip-flops in the device.
Central Global Rib
CCC
VersaTile Rows
Global Spine
Figure 2-23 * Example of Global Tree Use in an A3PN250 Device for Clock Routing
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ProASIC3 nano DC and Switching Characteristics
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard-dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-57. Table 2-67 to Table 2-72 on page 2-56 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading.
Timing Characteristics
Table 2-67 * A3PN010 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter Description tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.
-1
2
Std.
2
Min.
1
Max. 0.79 0.84
Min. 0.69 0.70
1
Max. 0.90 0.96
Min.
1
Max. 2 Units 1.06 1.12 ns ns ns ns
Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
0.60 0.62
0.81 0.82
0.22
0.26
0.30
ns MHz
Table 2-68 * A3PN015 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter Description tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.
-1
Std.
Min. 1 Max. 2 Min. 1 Max. 2 Min. 1 Max. 2 Units 0.66 0.67 0.91 0.96 0.75 0.77 1.04 1.10 0.89 0.90 1.22 1.29 ns ns ns ns 0.29 0.33 0.39 ns MHz
Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
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ProASIC3 nano Flash FPGAs Table 2-69 * A3PN020 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter Description tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.
-1
2
Std.
2
Min.
1
Max. 0.91 0.96
Min.
1
Max. 1.04 1.10
Min.
1
Max. 2 Units 1.22 1.29 ns ns ns ns
Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
0.66 0.67
0.75 0.77
0.89 0.90
0.29
0.33
0.39
ns MHz
Table 2-70 * A3PN060 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter Description tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.
-1
Std.
Min. 1 Max. 2 Min. 1 Max. 2 Min. 1 Max. 2 Units 0.72 0.71 0.91 0.94 0.82 0.81 1.04 1.07 0.96 0.96 1.22 1.26 ns ns ns ns 0.23 0.26 0.31 ns MHz
Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
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ProASIC3 nano DC and Switching Characteristics Table 2-71 * A3PN125 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter Description tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.
-1
2
Std.
2
Min.
1
Max. 0.99 1.02
Min.
1
Max. 1.12 1.17
Min.
1
Max. 2 Units 1.32 1.37 ns ns ns ns
Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
0.76 0.76
0.87 0.87
1.02 1.02
0.26
0.30
0.35
ns MHz
Table 2-72 * A3PN250 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V -2 Parameter Description tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.
-1
Std.
Min. 1 Max. 2 Min. 1 Max. 2 Min. 1 Max. 2 Units 0.79 0.78 1.02 1.04 0.90 0.88 1.16 1.18 1.06 1.04 1.36 1.39 ns ns ns ns 0.26 0.30 0.35 ns MHz
Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
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Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-73 * ProASIC3 nano CCC/PLL Specification Parameter Clock Conditioning Circuitry Input Frequency fIN_CCC Clock Conditioning Circuitry Output Frequency fOUT_CCC Delay Increments in Programmable Delay Blocks 1,2 Number of Programmable Values in Each Programmable Delay Block Serial Clock (SCLK) for Dynamic PLL 3,4 Input Cycle-to-Cycle Jitter (peak magnitude) Acquisition Time LockControl = 0 LockControl = 1 Tracking Jitter 6 LockControl = 0 LockControl = 1 Output Duty Cycle Delay Range in Block: Programmable Delay 1 1,2 Delay Range in Block: Programmable Delay 2 1,2 Delay Range in Block: Fixed Delay 1,2 VCO Output Peak-to-Peak Period Jitter 0.75 MHz to 50MHz 50 MHz to 250 MHz 250 MHz to 350 MHz Notes:
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-5 for deratings. 2. TJ = 25C, VCC = 1.5 V 3. Maximum value obtained for a -2 speed-grade device in worst-case commercial conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 4. The A3PN010, A3PN015, and A3PN020 devices do not support PLLs. 5. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying the VCO period by the % jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output divider settings. 6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. 7. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.425 V, VCCI = 3.3 , VQ/PQ/TQ type of packages, 20 pF load. 8. SSOs are outputs that are synchronous to a single clock domain, and have their clock-to-out times within 200 ps of each other.
Minimum 1.5 0.75
Typical
Maximum 350 350
Units MHz MHz ps
200 32 125 1.5 300 6.0 1.6 0.8 48.5 1.25 0.025 2.2 51.5 15.65 15.65
MHz ns s ms ns ns % ns ns ns
5,7,8
FCCC_OUT5
Max Peak-to-Peak Jitter Data SSO 2 0.50% 1.00% 2.50% SSO 4 0.50% 3.00% 4.00% SSO 8 0.70% 5.00% 6.00%
SSO 16 1.00% 9.00% 12.00%
Revision 8
2- 57
ProASIC3 nano DC and Switching Characteristics
Output Signal
Tperiod_max
Tperiod_min
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max - Tperiod_min. Figure 2-24 * Peak-to-Peak Jitter Definition
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ProASIC3 nano Flash FPGAs
Embedded SRAM and FIFO Characteristics
SRAM
RAM4K9 ADDRA11 ADDRA10 ADDRA0 DINA8 DINA7 DOUTA8 DOUTA7 DOUTA0 RAM512X18 RADDR8 RADDR7 RADDR0 RD17 RD16 RD0
DINA0
RW1 RW0
WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DOUTB8 DOUTB7 DOUTB0
PIPE
REN RCLK WADDR8 WADDR7
WADDR0 WD17 WD16
WD0 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB RESET WW1 WW0
WEN WCLK RESET
Figure 2-25 * RAM Models
Revision 8
2- 59
ProASIC3 nano DC and Switching Characteristics
Timing Waveforms
tCYC tCKH CLK tAS ADD A0 tBKS BLK_B tENS WEN_B tCKQ1 DO Dn D0 tDOH1
Figure 2-26 * RAM Read for Pass-Through Output
tCKL
tAH A1 A2 tBKH tENH
D1
D2
tCYC tCKH CLK t ADD tBKS BLK_B tENS WEN_B tCKQ2 DO Dn D0 tDOH2
Figure 2-27 * RAM Read for Pipelined Output
AS
tCKL
tAH A0 A1 A2 tBKH tENH
D1
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ProASIC3 nano Flash FPGAs
tCYC tCKH CLK tAS ADD A0 tBKS tBKH BLK_B tENS WEN_B tDS DI DI0 tDH DI1 tENH tAH A1 A2 tCKL
DO
Dn
D2
Figure 2-28 * RAM Write, Output Retained (WMODE = 0)
tCYC tCKH CLK tAS ADD A0 tBKS BLK_B tENS WEN_B tDS DI DO (pass-through) DO (pipelined) DI0 tDH DI1 DI2 tBKH tAH A1 A2 tCKL
Dn
DI0
DI1
Dn
DI0
DI1
Figure 2-29 * RAM Write, Output as Write Data (WMODE = 1)
Revision 8
2- 61
ProASIC3 nano DC and Switching Characteristics
tCYC tCKH CLK tCKL
RESET_B tRSTBQ DO Dm Dn
Figure 2-30 * RAM Reset
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ProASIC3 nano Flash FPGAs
Timing Characteristics
Table 2-74 * RAM4K9 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tAS tAH tENS tENH tBKS tBKH tDS tDH tCKQ1 Address Setup time Address Hold time REN_B, WEN_B Setup time REN_B, WEN_B Hold time BLK_B Setup time BLK_B Hold time Input data (DI) Setup time Input data (DI) Hold time Clock High to New Data Valid on DO (output retained, WMODE = 0) Clock High to New Data Valid on DO (flow-through, WMODE = 1) tCKQ2 tC2CWWL tC2CWWH tC2CRWH tC2CWRH tRSTBQ Clock High to New Data Valid on DO (pipelined) Description -2 0.25 0.00 0.14 0.10 0.23 0.02 0.18 0.00 1.79 2.36 0.89 -1 0.28 0.00 0.16 0.11 0.27 0.02 0.21 0.00 2.03 2.68 1.02 0.28 0.26 0.38 0.42 1.05 1.05 0.33 1.71 0.24 3.68 272 Std. Units 0.33 0.00 0.19 0.13 0.31 0.02 0.25 0.00 2.39 3.15 1.20 0.25 0.23 0.34 0.37 1.23 1.23 0.38 2.01 0.29 4.32 231 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Address collision clk-to-clk delay for reliable write after write on same 0.33 address; applicable to closing edge Address collision clk-to-clk delay for reliable write after write on same 0.30 address; applicable to rising edge Address collision clk-to-clk delay for reliable read access after write on same 0.45 address; applicable to opening edge Address collision clk-to-clk delay for reliable write access after read on same 0.49 address; applicable to opening edge RESET_B Low to Data Out Low on DO (flow through) RESET_B Low to Data Out Low on DO (pipelined) 0.92 0.92 0.29 1.50 0.21 3.23 310
tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX
RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle time Maximum Frequency
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
Revision 8
2- 63
ProASIC3 nano DC and Switching Characteristics Table 2-75 * RAM512X18 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tAS tAH tENS tENH tDS tDH tCKQ1 tCKQ2 tC2CRWH tC2CWRH tRSTBQ Address setup time Address hold time REN_B, WEN_B setup time REN_B, WEN_B hold time Input data (DI) setup time Input data (DI) hold time Clock HIGH to new data valid on DO (output retained, WMODE = 0) Clock HIGH to new data valid on DO (pipelined) Description -2 -1 Std. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
0.25 0.28 0.33 0.00 0.00 0.00 0.09 0.10 0.12 0.06 0.07 0.08 0.18 0.21 0.25 0.00 0.00 0.00 2.16 2.46 2.89 0.90 1.02 1.20
Address collision clk-to-clk delay for reliable read access after write on same 0.50 0.43 0.38 address; applicable to opening edge Address collision clk-to-clk delay for reliable write access after read on same 0.59 0.50 0.44 address; applicable to opening edge RESET_B LOW to data out LOW on DO (flow-through) RESET_B LOW to data out LOW on DO (pipelined) 0.92 1.05 1.23 0.92 1.05 1.23 0.29 0.33 0.38 1.50 1.71 2.01 0.21 0.24 0.29 3.23 3.68 4.32 310 272
tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX
RESET_B removal RESET_B recovery RESET_B minimum pulse width Clock cycle time Maximum frequency
231 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
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ProASIC3 nano Flash FPGAs
FIFO
FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP AEVAL11 AEVAL10 RD17 RD16
RD0 FULL AFULL EMPTY AEMPTY
AEVAL0 AFVAL11 AFVAL10
AFVAL0 REN RBLK RCLK WD17 WD16
WD0 WEN WBLK WCLK RPIPE
RESET
Figure 2-31 * FIFO Model
Revision 8
2- 65
ProASIC3 nano DC and Switching Characteristics
Timing Waveforms
RCLK/ WCLK tMPWRSTB RESET_B tRSTFG EMPTY tRSTAF AEMPTY tRSTFG FULL tRSTAF AFULL WA/RA (Address Counter)
Figure 2-32 * FIFO Reset
tRSTCK
MATCH (A0)
tCYC
RCLK
tRCKEF EMPTY
tCKAF
AEMPTY WA/RA (Address Counter) NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
Figure 2-33 * FIFO EMPTY Flag and AEMPTY Flag Assertion
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ProASIC3 nano Flash FPGAs
tCYC WCLK tWCKFF FULL tCKAF AFULL
WA/RA NO MATCH (Address Counter)
NO MATCH
Dist = AFF_TH
MATCH (FULL)
Figure 2-34 * FIFO FULL Flag and AFULL Flag Assertion
WCLK
WA/RA MATCH (Address Counter) (EMPTY)
NO MATCH
NO MATCH 2nd Rising Edge After 1st Write tRCKEF
NO MATCH
NO MATCH
Dist = AEF_TH + 1
RCLK
1st Rising Edge After 1st Write
EMPTY tCKAF AEMPTY
Figure 2-35 * FIFO EMPTY Flag and AEMPTY Flag Deassertion
RCLK WA/RA (Address Counter)
MATCH (FULL) NO MATCH NO MATCH NO MATCH NO MATCH Dist = AFF_TH - 1
WCLK
1st Rising Edge After 1st Read
1st Rising Edge After 2nd Read tWCKF
FULL tCKAF AFULL
Figure 2-36 * FIFO FULL Flag and AFULL Flag Deassertion
Revision 8
2- 67
ProASIC3 nano DC and Switching Characteristics
Timing Characteristics
Table 2-76 * FIFO Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ Description REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock HIGH to New Data Valid on DO (flow-through) Clock HIGH to New Data Valid on DO (pipelined) RCLK HIGH to Empty Flag Valid WCLK HIGH to Full Flag Valid Clock HIGH to Almost Empty/Full Flag Valid RESET_B LOW to Empty/Full Flag Valid RESET_B LOW to Almost Empty/Full Flag Valid RESET_B LOW to Data Out LOW on DO (flow-through) RESET_B LOW to Data Out LOW on DO (pipelined) tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency for FIFO -2 1.38 0.02 0.22 0.00 0.18 0.00 2.36 0.89 1.72 1.63 6.19 1.69 6.13 0.92 0.92 0.29 1.50 0.21 3.23 310 -1 1.57 0.02 0.25 0.00 0.21 0.00 2.68 1.02 1.96 1.86 7.05 1.93 6.98 1.05 1.05 0.33 1.71 0.24 3.68 272 Std. 1.84 0.02 0.30 0.00 0.25 0.00 3.15 1.20 2.30 2.18 8.29 2.27 8.20 1.23 1.23 0.38 2.01 0.29 4.32 231 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
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ProASIC3 nano Flash FPGAs
Embedded FlashROM Characteristics
tSU CLK tHOLD tSU tHOLD tSU tHOLD
Address
A0 tCKQ2
A1 tCKQ2 D0 tCKQ2 D1
Data
D0
Figure 2-37 * Timing Diagram
Timing Characteristics
Table 2-77 * Embedded FlashROM Access Time Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tSU tHOLD tCK2Q FMAX Description Address Setup Time Address Hold Time Clock to Out Maximum Clock Frequency -2 0.53 0.00 16.23 15.00 -1 0.61 0.00 18.48 15.00 Std. 0.71 0.00 21.73 15.00 Units ns ns ns MHz
Revision 8
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ProASIC3 nano DC and Switching Characteristics
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-12 for more details. Timing Characteristics Table 2-78 * JTAG 1532 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tDISU tDIHD tTMSSU tTMDHD tTCK2Q tRSTB2Q FTCKMAX tTRSTREM tTRSTREC tTRSTMPW Description Test Data Input Setup Time Test Data Input Hold Time Test Mode Select Setup Time Test Mode Select Hold Time Clock to Q (data out) Reset to Q (data out) TCK Maximum Frequency ResetB Removal Time ResetB Recovery Time ResetB Minimum Pulse -2 0.53 1.07 0.53 1.07 6.39 21.31 23.00 0.00 0.21 TBD -1 0.60 1.21 0.60 1.21 7.24 24.15 20.00 0.00 0.24 TBD Std. 0.71 1.42 0.71 1.42 8.52 28.41 17.00 0.00 0.28 TBD Units ns ns ns ns ns ns MHz ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Actel Safety Critical, Life Support, and High-Reliability Applications Policy
The Actel products described in this advance status datasheet may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information.
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ProASIC3 nano Flash FPGAs
3 - Package Pin Assignments
48-Pin QFN
Pin 1 48 1
Notes:
1. This is the bottom view of the package. 2. The die attach paddle of the package is tied to ground (GND).
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
Revision 8
3 -1
Package Pin Assignments
48-Pin QFN Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A3PN010 Function GEC0/IO37RSB1 IO36RSB1 GEA0/IO34RSB1 IO22RSB1 GND VCCIB1 IO24RSB1 IO33RSB1 IO26RSB1 IO32RSB1 IO27RSB1 IO29RSB1 IO30RSB1 IO31RSB1 IO28RSB1 IO25RSB1 IO23RSB1 VCC VCCIB1 IO17RSB1 IO14RSB1 TCK TDI TMS VPUMP TDO TRST VJTAG IO11RSB0 IO10RSB0 IO09RSB0 IO08RSB0 VCCIB0 GND VCC
48-Pin QFN Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 A3PN010 Function IO07RSB0 IO06RSB0 GDA0/IO05RSB0 IO03RSB0 GDC0/IO01RSB0 IO12RSB1 IO13RSB1 IO15RSB1 IO16RSB1 IO18RSB1 IO19RSB1 IO20RSB1 IO21RSB1
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ProASIC3 nano Flash FPGAs
48-Pin QFN Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A3PN030Z Function IO82RSB1 GEC0/IO73RSB1 GEA0/IO72RSB1 GEB0/IO71RSB1 GND VCCIB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO62RSB1 IO61RSB1 IO60RSB1 IO57RSB1 IO55RSB1 IO53RSB1 VCC VCCIB1 IO46RSB1 IO42RSB1 TCK TDI TMS VPUMP TDO TRST VJTAG IO38RSB0 GDB0/IO34RSB0 GDA0/IO33RSB0 GDC0/IO32RSB0 VCCIB0 GND VCC
48-Pin QFN Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 A3PN030Z Function IO25RSB0 IO24RSB0 IO22RSB0 IO20RSB0 IO18RSB0 IO16RSB0 IO14RSB0 IO10RSB0 IO08RSB0 IO06RSB0 IO04RSB0 IO02RSB0 IO00RSB0
Revision 8
3 -3
Package Pin Assignments
68-Pin QFN
Pin A1 Mark
68 1
Notes:
1. This is the bottom view of the package. 2. The die attach paddle of the package is tied to ground (GND).
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
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ProASIC3 nano Flash FPGAs
68-Pin QFN Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3PN015 Function IO60RSB2 IO54RSB2 IO52RSB2 IO50RSB2 IO49RSB2 GEC0/IO48RSB2 GEA0/IO47RSB2 VCC GND VCCIB2 IO46RSB2 IO45RSB2 IO44RSB2 IO43RSB2 IO42RSB2 IO41RSB2 IO40RSB2 IO39RSB1 IO37RSB1 IO35RSB1 IO33RSB1 IO31RSB1 IO30RSB1 VCC GND VCCIB1 IO27RSB1 IO25RSB1 IO23RSB1 IO21RSB1 IO19RSB1 TCK TDI TMS VPUMP TDO
68-Pin QFN Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 A3PN015 Function TRST VJTAG IO17RSB0 IO16RSB0 GDA0/IO15RSB0 GDC0/IO14RSB0 IO13RSB0 VCCIB0 GND VCC IO12RSB0 IO11RSB0 IO09RSB0 IO05RSB0 IO00RSB0 IO07RSB0 IO03RSB0 IO18RSB1 IO20RSB1 IO22RSB1 IO24RSB1 IO28RSB1 NC GND NC IO32RSB1 IO34RSB1 IO36RSB1 IO61RSB2 IO58RSB2 IO56RSB2 IO63RSB2
Revision 8
3 -5
Package Pin Assignments
68-Pin QFN Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A3PN020 Function IO60RSB2 IO54RSB2 IO52RSB2 IO50RSB2 IO49RSB2 GEC0/IO48RSB2 GEA0/IO47RSB2 VCC GND VCCIB2 IO46RSB2 IO45RSB2 IO44RSB2 IO43RSB2 IO42RSB2 IO41RSB2 IO40RSB2 IO39RSB1 IO37RSB1 IO35RSB1 IO33RSB1 IO31RSB1 IO30RSB1 VCC GND VCCIB1 IO27RSB1 IO25RSB1 IO23RSB1 IO21RSB1 IO19RSB1 TCK TDI TMS VPUMP
68-Pin QFN Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 A3PN020 Function TDO TRST VJTAG IO17RSB0 IO16RSB0 GDA0/IO15RSB0 GDC0/IO14RSB0 IO13RSB0 VCCIB0 GND VCC IO12RSB0 IO11RSB0 IO09RSB0 IO05RSB0 IO00RSB0 IO07RSB0 IO03RSB0 IO18RSB1 IO20RSB1 IO22RSB1 IO24RSB1 IO28RSB1 NC GND NC IO32RSB1 IO34RSB1 IO36RSB1 IO61RSB2 IO58RSB2 IO56RSB2 IO63RSB2
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R e vi s i o n 8
ProASIC3 nano Flash FPGAs
68-Pin QFN Pin Number A3PN030Z Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 IO82RSB1 IO80RSB1 IO78RSB1 IO76RSB1 GEC0/IO73RSB1 GEA0/IO72RSB1 GEB0/IO71RSB1 VCC GND VCCIB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO63RSB1 IO62RSB1 IO60RSB1 IO58RSB1 IO56RSB1 IO54RSB1 IO52RSB1 IO51RSB1 VCC GND VCCIB1 IO50RSB1 IO48RSB1 IO46RSB1 IO44RSB1 IO42RSB1 TCK TDI TMS VPUMP TDO
68-Pin QFN Pin Number A3PN030Z Function 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 TRST VJTAG IO40RSB0 IO37RSB0 GDB0/IO34RSB0 GDA0/IO33RSB0 GDC0/IO32RSB0 VCCIB0 GND VCC IO31RSB0 IO29RSB0 IO28RSB0 IO27RSB0 IO25RSB0 IO24RSB0 IO22RSB0 IO21RSB0 IO19RSB0 IO17RSB0 IO15RSB0 IO14RSB0 VCCIB0 GND VCC IO12RSB0 IO10RSB0 IO08RSB0 IO06RSB0 IO04RSB0 IO02RSB0 IO00RSB0
Revision 8
3 -7
Package Pin Assignments
100-Pin VQFP
100
1
Note: This is the top view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
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ProASIC3 nano Flash FPGAs
100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A3PN030Z Function GND IO82RSB1 IO81RSB1 IO80RSB1 IO79RSB1 IO78RSB1 IO77RSB1 IO76RSB1 GND IO75RSB1 IO74RSB1 GEC0/IO73RSB1 GEA0/IO72RSB1 GEB0/IO71RSB1 IO70RSB1 IO69RSB1 VCC VCCIB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO63RSB1 IO62RSB1 IO61RSB1 IO60RSB1 IO59RSB1 IO58RSB1 IO57RSB1 IO56RSB1 IO55RSB1 IO54RSB1 IO53RSB1 IO52RSB1
100-Pin VQFP Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 A3PN030Z Function IO51RSB1 VCC GND VCCIB1 IO49RSB1 IO47RSB1 IO46RSB1 IO45RSB1 IO44RSB1 IO43RSB1 IO42RSB1 TCK TDI TMS NC GND VPUMP NC TDO TRST VJTAG IO41RSB0 IO40RSB0 IO39RSB0 IO38RSB0 IO37RSB0 IO36RSB0 GDB0/IO34RSB0 GDA0/IO33RSB0 GDC0/IO32RSB0 VCCIB0 GND VCC IO31RSB0 IO30RSB0
100-Pin VQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A3PN030Z Function IO29RSB0 IO28RSB0 IO27RSB0 IO26RSB0 IO25RSB0 IO24RSB0 IO23RSB0 IO22RSB0 IO21RSB0 IO20RSB0 IO19RSB0 IO18RSB0 IO17RSB0 IO16RSB0 IO15RSB0 IO14RSB0 VCCIB0 GND VCC IO12RSB0 IO10RSB0 IO08RSB0 IO07RSB0 IO06RSB0 IO05RSB0 IO04RSB0 IO03RSB0 IO02RSB0 IO01RSB0 IO00RSB0
Revision 8
3 -9
Package Pin Assignments
100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A3PN060 Function GND GAA2/IO51RSB1 IO52RSB1 GAB2/IO53RSB1 IO95RSB1 GAC2/IO94RSB1 IO93RSB1 IO92RSB1 GND GFB1/IO87RSB1 GFB0/IO86RSB1 VCOMPLF GFA0/IO85RSB1 VCCPLF GFA1/IO84RSB1 GFA2/IO83RSB1 VCC VCCIB1 GEC1/IO77RSB1 GEB1/IO75RSB1 GEB0/IO74RSB1 GEA1/IO73RSB1 GEA0/IO72RSB1 VMV1 GNDQ GEA2/IO71RSB1 GEB2/IO70RSB1 GEC2/IO69RSB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO63RSB1 IO62RSB1
100-Pin VQFP Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 A3PN060 Function IO61RSB1 VCC GND VCCIB1 IO60RSB1 IO59RSB1 IO58RSB1 IO57RSB1 GDC2/IO56RSB1 GDB2/IO55RSB1 GDA2/IO54RSB1 TCK TDI TMS VMV1 GND VPUMP NC TDO TRST VJTAG GDA1/IO49RSB0 GDC0/IO46RSB0 GDC1/IO45RSB0 GCC2/IO43RSB0 GCB2/IO42RSB0 GCA0/IO40RSB0 GCA1/IO39RSB0 GCC0/IO36RSB0 GCC1/IO35RSB0 VCCIB0 GND VCC IO31RSB0 GBC2/IO29RSB0
100-Pin VQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A3PN060 Function GBB2/IO27RSB0 IO26RSB0 GBA2/IO25RSB0 VMV0 GNDQ GBA1/IO24RSB0 GBA0/IO23RSB0 GBB1/IO22RSB0 GBB0/IO21RSB0 GBC1/IO20RSB0 GBC0/IO19RSB0 IO18RSB0 IO17RSB0 IO15RSB0 IO13RSB0 IO11RSB0 VCCIB0 GND VCC IO10RSB0 IO09RSB0 IO08RSB0 GAC1/IO07RSB0 GAC0/IO06RSB0 GAB1/IO05RSB0 GAB0/IO04RSB0 GAA1/IO03RSB0 GAA0/IO02RSB0 IO01RSB0 IO00RSB0
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ProASIC3 nano Flash FPGAs
100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A3PN060Z GND GAA2/IO51RSB1 IO52RSB1 GAB2/IO53RSB1 IO95RSB1 GAC2/IO94RSB1 IO93RSB1 IO92RSB1 GND GFB1/IO87RSB1 GFB0/IO86RSB1 VCOMPLF GFA0/IO85RSB1 VCCPLF GFA1/IO84RSB1 GFA2/IO83RSB1 VCC VCCIB1 GEC1/IO77RSB1 GEB1/IO75RSB1 GEB0/IO74RSB1 GEA1/IO73RSB1 GEA0/IO72RSB1 VMV1 GNDQ GEA2/IO71RSB1 GEB2/IO70RSB1 GEC2/IO69RSB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO63RSB1 IO62RSB1 Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
100-Pin VQFP A3PN060Z IO61RSB1 VCC GND VCCIB1 IO60RSB1 IO59RSB1 IO58RSB1 IO57RSB1 GDC2/IO56RSB1 GDB2/IO55RSB1 GDA2/IO54RSB1 TCK TDI TMS VMV1 GND VPUMP NC TDO TRST VJTAG GDA1/IO49RSB0 GDC0/IO46RSB0 GDC1/IO45RSB0 GCC2/IO43RSB0 GCB2/IO42RSB0 GCA0/IO40RSB0 GCA1/IO39RSB0 GCC0/IO36RSB0 GCC1/IO35RSB0 VCCIB0 GND VCC IO31RSB0 GBC2/IO29RSB0 Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
100-Pin VQFP A3PN060Z GBB2/IO27RSB0 IO26RSB0 GBA2/IO25RSB0 VMV0 GNDQ GBA1/IO24RSB0 GBA0/IO23RSB0 GBB1/IO22RSB0 GBB0/IO21RSB0 GBC1/IO20RSB0 GBC0/IO19RSB0 IO18RSB0 IO17RSB0 IO15RSB0 IO13RSB0 IO11RSB0 VCCIB0 GND VCC IO10RSB0 IO09RSB0 IO08RSB0 GAC1/IO07RSB0 GAC0/IO06RSB0 GAB1/IO05RSB0 GAB0/IO04RSB0 GAA1/IO03RSB0 GAA0/IO02RSB0 IO01RSB0 IO00RSB0
Revision 8
3- 11
Package Pin Assignments
100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A3PN125 Function GND GAA2/IO67RSB1 IO68RSB1 GAB2/IO69RSB1 IO132RSB1 GAC2/IO131RSB1 IO130RSB1 IO129RSB1 GND GFB1/IO124RSB1 GFB0/IO123RSB1 VCOMPLF GFA0/IO122RSB1 VCCPLF GFA1/IO121RSB1 GFA2/IO120RSB1 VCC VCCIB1 GEC0/IO111RSB1 GEB1/IO110RSB1 GEB0/IO109RSB1 GEA1/IO108RSB1 GEA0/IO107RSB1 VMV1 GNDQ GEA2/IO106RSB1 GEB2/IO105RSB1 GEC2/IO104RSB1 IO102RSB1 IO100RSB1 IO99RSB1 IO97RSB1 IO96RSB1 IO95RSB1 IO94RSB1
100-Pin VQFP Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 A3PN125 Function IO93RSB1 VCC GND VCCIB1 IO87RSB1 IO84RSB1 IO81RSB1 IO75RSB1 GDC2/IO72RSB1 GDB2/IO71RSB1 GDA2/IO70RSB1 TCK TDI TMS VMV1 GND VPUMP NC TDO TRST VJTAG GDA1/IO65RSB0 GDC0/IO62RSB0 GDC1/IO61RSB0 GCC2/IO59RSB0 GCB2/IO58RSB0 GCA0/IO56RSB0 GCA1/IO55RSB0 GCC0/IO52RSB0 GCC1/IO51RSB0 VCCIB0 GND VCC IO47RSB0 GBC2/IO45RSB0
100-Pin VQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A3PN125 Function GBB2/IO43RSB0 IO42RSB0 GBA2/IO41RSB0 VMV0 GNDQ GBA1/IO40RSB0 GBA0/IO39RSB0 GBB1/IO38RSB0 GBB0/IO37RSB0 GBC1/IO36RSB0 GBC0/IO35RSB0 IO32RSB0 IO28RSB0 IO25RSB0 IO22RSB0 IO19RSB0 VCCIB0 GND VCC IO15RSB0 IO13RSB0 IO11RSB0 IO09RSB0 IO07RSB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0
3- 12
R e visio n 8
ProASIC3 nano Flash FPGAs
100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A3PN125Z Function GND GAA2/IO67RSB1 IO68RSB1 GAB2/IO69RSB1 IO132RSB1 GAC2/IO131RSB1 IO130RSB1 IO129RSB1 GND GFB1/IO124RSB1 GFB0/IO123RSB1 VCOMPLF GFA0/IO122RSB1 VCCPLF GFA1/IO121RSB1 GFA2/IO120RSB1 VCC VCCIB1 GEC0/IO111RSB1 GEB1/IO110RSB1 GEB0/IO109RSB1 GEA1/IO108RSB1 GEA0/IO107RSB1 VMV1 GNDQ GEA2/IO106RSB1 GEB2/IO105RSB1 GEC2/IO104RSB1 IO102RSB1 IO100RSB1 IO99RSB1 IO97RSB1 IO96RSB1 IO95RSB1 IO94RSB1
100-Pin VQFP Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 A3PN125Z Function IO93RSB1 VCC GND VCCIB1 IO87RSB1 IO84RSB1 IO81RSB1 IO75RSB1 GDC2/IO72RSB1 GDB2/IO71RSB1 GDA2/IO70RSB1 TCK TDI TMS VMV1 GND VPUMP NC TDO TRST VJTAG GDA1/IO65RSB0 GDC0/IO62RSB0 GDC1/IO61RSB0 GCC2/IO59RSB0 GCB2/IO58RSB0 GCA0/IO56RSB0 GCA1/IO55RSB0 GCC0/IO52RSB0 GCC1/IO51RSB0 VCCIB0 GND VCC IO47RSB0 GBC2/IO45RSB0
100-Pin VQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A3PN125Z Function GBB2/IO43RSB0 IO42RSB0 GBA2/IO41RSB0 VMV0 GNDQ GBA1/IO40RSB0 GBA0/IO39RSB0 GBB1/IO38RSB0 GBB0/IO37RSB0 GBC1/IO36RSB0 GBC0/IO35RSB0 IO32RSB0 IO28RSB0 IO25RSB0 IO22RSB0 IO19RSB0 VCCIB0 GND VCC IO15RSB0 IO13RSB0 IO11RSB0 IO09RSB0 IO07RSB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0
Revision 8
3- 13
Package Pin Assignments
100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3PN250 Function GND GAA2/IO67RSB3 IO66RSB3 GAB2/IO65RSB3 IO64RSB3 GAC2/IO63RSB3 IO62RSB3 IO61RSB3 GND GFB1/IO60RSB3 GFB0/IO59RSB3 VCOMPLF GFA0/IO57RSB3 VCCPLF GFA1/IO58RSB3 GFA2/IO56RSB3 VCC VCCIB3 GFC2/IO55RSB3 GEC1/IO54RSB3 GEC0/IO53RSB3 GEA1/IO52RSB3 GEA0/IO51RSB3 VMV3 GNDQ GEA2/IO50RSB2 GEB2/IO49RSB2 GEC2/IO48RSB2 IO47RSB2 IO46RSB2 IO45RSB2 IO44RSB2 IO43RSB2 IO42RSB2 IO41RSB2 IO40RSB2
100-Pin VQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3PN250 Function VCC GND VCCIB2 IO39RSB2 IO38RSB2 IO37RSB2 GDC2/IO36RSB2 GDB2/IO35RSB2 GDA2/IO34RSB2 GNDQ TCK TDI TMS VMV2 GND VPUMP NC TDO TRST VJTAG GDA1/IO33RSB1 GDC0/IO32RSB1 GDC1/IO31RSB1 IO30RSB1 GCB2/IO29RSB1 GCA1/IO27RSB1 GCA0/IO28RSB1 GCC0/IO26RSB1 GCC1/IO25RSB1 VCCIB1 GND VCC IO24RSB1 GBC2/IO23RSB1 GBB2/IO22RSB1 IO21RSB1
100-Pin VQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A3PN250 Function GBA2/IO20RSB1 VMV1 GNDQ GBA1/IO19RSB0 GBA0/IO18RSB0 GBB1/IO17RSB0 GBB0/IO16RSB0 GBC1/IO15RSB0 GBC0/IO14RSB0 IO13RSB0 IO12RSB0 IO11RSB0 IO10RSB0 IO09RSB0 VCCIB0 GND VCC IO08RSB0 IO07RSB0 IO06RSB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0 GNDQ VMV0
3- 14
R e visio n 8
ProASIC3 nano Flash FPGAs
100-Pin VQFP Pin Number A3PN250Z Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 GND GAA2/IO67RSB3 IO66RSB3 GAB2/IO65RSB3 IO64RSB3 GAC2/IO63RSB3 IO62RSB3 IO61RSB3 GND GFB1/IO60RSB3 GFB0/IO59RSB3 VCOMPLF GFA0/IO57RSB3 VCCPLF GFA1/IO58RSB3 GFA2/IO56RSB3 VCC VCCIB3 GFC2/IO55RSB3 GEC1/IO54RSB3 GEC0/IO53RSB3 GEA1/IO52RSB3 GEA0/IO51RSB3 VMV3 GNDQ GEA2/IO50RSB2 GEB2/IO49RSB2 GEC2/IO48RSB2 IO47RSB2 IO46RSB2 IO45RSB2 IO44RSB2 IO43RSB2 IO42RSB2 IO41RSB2 IO40RSB2
100-Pin VQFP Pin Number A3PN250Z Function 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VCC GND VCCIB2 IO39RSB2 IO38RSB2 IO37RSB2 GDC2/IO36RSB2 GDB2/IO35RSB2 GDA2/IO34RSB2 GNDQ TCK TDI TMS VMV2 GND VPUMP NC TDO TRST VJTAG GDA1/IO33RSB1 GDC0/IO32RSB1 GDC1/IO31RSB1 IO30RSB1 GCB2/IO29RSB1 GCA1/IO27RSB1 GCA0/IO28RSB1 GCC0/IO26RSB1 GCC1/IO25RSB1 VCCIB1 GND VCC IO24RSB1 GBC2/IO23RSB1 GBB2/IO22RSB1 IO21RSB1
100-Pin VQFP Pin Number A3PN250Z Function 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 GBA2/IO20RSB1 VMV1 GNDQ GBA1/IO19RSB0 GBA0/IO18RSB0 GBB1/IO17RSB0 GBB0/IO16RSB0 GBC1/IO15RSB0 GBC0/IO14RSB0 IO13RSB0 IO12RSB0 IO11RSB0 IO10RSB0 IO09RSB0 VCCIB0 GND VCC IO08RSB0 IO07RSB0 IO06RSB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0 GNDQ VMV0
Revision 8
3- 15
4 - Datasheet Information
List of Changes
The following table lists critical changes that were made in each revision of the ProASIC3 nano datasheet. Revision July 2010 Changes The versioning system for datasheets has been changed. Datasheets are assigned a revision number that increments each time the datasheet is revised. The "ProASIC3 nano Device Status" table on page II indicates the status for each device in the device family. References to differential inputs were removed from the datasheet, since ProASIC3 nano devices do not support differential inputs (SAR 21449). The "ProASIC3 nano Device Status" table is new. The JTAG DC voltage was revised in Table 2-2 * Recommended Operating Conditions 1, 2 (SAR 24052). The maximum value for VPUMP programming voltage (operation mode) was changed from 3.45 V to 3.6 V (SAR 25220). The highest temperature in Table 2-6 * Temperature and Voltage Derating Factors for Timing Delays was changed to 100C. The typical value for A3PN010 was revised in Table 2-7 * Quiescent Supply Current Characteristics. The note was revised to remove the statement that values do not include I/O static contribution. The following tables were updated with available information: Table 2-8 * Summary of I/O Input Buffer Power (Per Pin) - Default I/O Software Settings Table 2-9 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings1 Table 2-10 * Different Components Contributing to Dynamic Power Consumption in ProASIC3 nano Devices Table 2-14 * Summary of Maximum and Minimum DC Input and Output Levels Table 2-18 * Summary of I/O Timing Characteristics--Software Default Settings (at 35 pF) Table 2-19 * Summary of I/O Timing Characteristics--Software Default Settings (at 10 pF) Table 2-22 * I/O Weak Pull-Up/Pull-Down Resistances was revised to add wide range data and correct the formulas in the table notes (SAR 21348). The text introducing Table 2-24 * Duration of Short Circuit Event before Failure was revised to state six months at 100 instead of three months at 110 for reliability concerns. The row for 110 was removed from the table. Table 2-26 * I/O Input Rise Time, Fall Time, and Related I/O Reliability was revised to give values with Schmitt trigger disabled and enabled (SAR 24634). The temperature for reliability was changed to 100C. Table 2-33 * Minimum and Maximum DC Input and Output Levels for 3.3 V LVCMOS Wide Range and the timing tables in the "Single-Ended I/O Characteristics" section were updated with available information. The timing tables for 3.3 V LVCMOS wide range are new. 2-19 2-20 Page N/A
Revision 8 (Apr 2010)
N/A II 2-2
2-5 2-6
2-6 through 2-18
2-21
2-22
Revision 8
4 -1
Datasheet Information
Revision Revision 8 (cont'd)
Changes The following sentence was deleted from the "2.5 V LVCMOS" section: "It uses a 5 V-tolerant input buffer and push-pull output buffer."
Page 2-30
Values for tDDRISUD and FDDRIMAX were updated in Table 2-62 * Input DDR 2-46, 2-48 Propagation Delays. Values for FDDOMAX were added to Table 2-64 * Output DDR Propagation Delays (SAR 23919). Table 2-67 * A3PN010 Global Resource through Table 2-70 * A3PN060 Global Resource were updated with available information. Table 2-73 * ProASIC3 nano CCC/PLL Specification was revised (SAR 79390). All product tables and pin tables were updated to show clearly that A3PN030 is Product Brief Advance available only in the Z feature at this time, as A3PN030Z. The nano-Z feature grade devices are designated with a Z at the end of the part number. v0.7 Packaging Advance v0.6 The "68-Pin QFN" and "100-Pin VQFP" pin tables for A3PN030 were removed. Only the Z grade for A3PN030 is available at this time. Revision 7 (Jan 2010) 2-54 through 2-55 2-57 N/A
N/A I
Revision 6 (Aug 2009) The note for A3PN030 in the "ProASIC3 nano Devices" table was revised. It Product Brief Advance states A3PN030 is available in the Z feature grade only. v0.6 Packaging v0.5 Advance The "68-Pin QFN" pin table for A3PN030 is new. The "48-Pin QFN", "68-Pin QFN", and "100-Pin VQFP" pin tables for A3PN030Z are new. The "100-Pin VQFP" pin table for A3PN060Z is new. The "100-Pin VQFP" pin table for A3PN125Z is new The "100-Pin VQFP" pin table for A3PN250Z is new. Revision 5 (Mar 2009) All references to speed grade -F were removed from this document. Product Brief Advance The"I/Os with Advanced I/O Standards" section was revised to add definitions of v0.5 hot-swap and cold-sparing. Revision 4 (Feb 2009) The "100-Pin VQFP" pin table for A3PN030 is new. Packaging Advance v0.4 Revision 3 (Feb 2009) The "100-Pin QFN" section was removed. Packaging Advance v0.3 Revision 2 (Nov 2008) The "ProASIC3 nano Devices" table was revised to change the maximum user Product Brief Advance I/Os for A3PN020 and A3PN030. The following table note was removed: "Six chip (main) and three quadrant global networks are available for A3PN060 and v0.4 above." The QN100 package was removed for all devices. The "Device Marking" section is new. Revision 1 (Oct 2008) The A3PN030 device was added to product tables and replaces A3P030 entries Product Brief Advance that were formerly in the tables. v0.3 The "Wide Range I/O Support" section is new.
3-7 3-3, 3-7, 3-9 3-11 3-13 3-15 N/A 1-7 3-10
N/A
I
N/A III I to IV
1-7
4-2
R e vi s i o n 8
ProASIC3 nano Flash FPGAs
Revision Revision 1 (cont'd)
Changes The "I/Os Per Package" table was updated to add the following information to table note 4: "For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other packages are RoHS-compliant only." The "ProASIC3 nano Product Available in the Z Feature Grade" section was updated to remove QN100 for A3PN250. The "General Description" section was updated to give correct information about number of gates and dual-port RAM for ProASIC3 nano devices. The device architecture figures, Figure 1-3 * ProASIC3 nano Device Architecture Overview with Two I/O Banks (A3PN060 and A3PN125) through Figure 1-4 * ProASIC3 nano Device Architecture Overview with Four I/O Banks (A3PN250), were revised. Figure 1-1 * ProASIC3 Device Architecture Overview with Two I/O Banks and No RAM (A3PN010 and A3PN030) is new. The "PLL and CCC" section was revised to include information about CCC-GLs in A3PN020 and smaller devices.
Page II
IV 1-1 1-3 through 1-4
1-6 2-2
DC and Switching Characteristics Advance v0.2
Table 2-2 * Recommended Operating Conditions 1, 2 was revised to add VMV to the VCCI row. The following table note was added: "VMV pins must be connected to the corresponding VCCI pins." The values in Table 2-7 * Quiescent Supply Current Characteristics were revised for A3PN010, A3PN015, and A3PN020.
2-6
A table note, "All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide 2-16, 2-18 range, as specified in the JESD8-B specification," was added to Table 2-14 * Summary of Maximum and Minimum DC Input and Output Levels, Table 2-18 * Summary of I/O Timing Characteristics--Software Default Settings (at 35 pF), and Table 2-19 * Summary of I/O Timing Characteristics--Software Default Settings (at 10 pF). 3.3 V LVCMOS Wide Range was added to Table 2-21 * I/O Output Buffer 2-19, 2-20 Maximum Resistances 1 and Table 2-23 * I/O Short Currents IOSH/IOSL. Packaging Advance v0.2 The "48-Pin QFN" pin diagram was revised. Note 2 for the "48-Pin QFN", "68-Pin QFN", and "100-Pin VQFP" pin diagrams was added/changed to "The die attach paddle of the package is tied to ground (GND)." The "100-Pin VQFP" pin diagram was revised to move the pin IDs to the upper left corner instead of the upper right corner. 3-2 3-2, 3-5, 3-9 3-9
Revision 8
4 -3
Datasheet Information
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "ProASIC3 nano Device Status" table on page II, is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible.
Unmarked (production)
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States.
Actel Safety Critical, Life Support, and High-Reliability Applications Policy
The Actel products described in this advance status document may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information.
4-4
R e vi s i o n 8
Actel is the leader in low power FPGAs and mixed signal FPGAs and offers the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com. Actel Corporation
2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600
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